Neural Network ATPG

chickenchairwomanAI and Robotics

Oct 19, 2013 (3 years and 7 months ago)

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4/28/05

Sinha: EE7250

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Neural Network ATPG

By

Priyanka Sinha

Class Presentation


VLSI Testing Spring 2005

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Sinha: EE7250

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Layout of Talk


What is a neural network


Represent a circuit


Inject a fault in a circuit


Generate a test for the circuit


Brief summary of fast ATPG


References

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Sinha: EE7250

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What is a neural network?

E =
-
1/2*(sum_i_1
-
N(sum_j_1
-
N(T(i,j)*V(i)*V(j)))


sum_i_1
-
N(I(i)*V(i))

V(i) = 1 if Sum_j_1
-
N(T(i,j)*V(j)) + I(i) >0


0


if if Sum_j_1
-
N(T(i,j)*V(j)) + I(i) <0


V(i) otherwise

4/28/05

Sinha: EE7250

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Circuit as neural network

AND

T(i,j) = (1
-

delta
(i,j)) X ((A+B) X
connected(i,j)


B X inputs(i,j)

I(i) =
-
(2A+B) X output(i)

K = 0

OR

T(i,j) = (1
-

delta
(i,j)) X ((A+B) X
connected(i,j)


B X inputs(i,j)

I(i) =
-
B X output(i)


A X input(i)

K = 0

NAND

T(i,j) = (1
-

delta
(i,j)) X ((
-
A
-
B) X
connected(i,j)


B X inputs(i,j)

I(i) = (2A+B) X output(i) + (A+B) X input(i)

K = 2A+B

NOR

T(i,j) = (1
-

delta
(i,j)) X ((
-
A
-
B) X
connected(i,j)


B X inputs(i,j)

I(i) = B

K = B

NOT

T(i,j) = (1


delta(i,j)) X 2J

I(i) = J

K = J

i

4/28/05

Sinha: EE7250

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Circuit as neural network

inputs(i,j)

1 if i and j are input neurons for
the same gate

0 otherwise

connected(i,j)

1


inputs(i,j)

delta(i,j)

1
If i=j

0 otherwise

output(i)

1
if I is an output neuron for the
gate

0 otherwise

input(i)

1
if I is an output neuron for the
gate

0 otherwise

4/28/05

Sinha: EE7250

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Circuit as a neural network

Let

A = 2

B = 2

J=2

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Inject fault in circuit

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Generate test for circuit


Minimize Energy of network


Gradient descent technique


E(k) = E(V(k) = 0)


E(V(k) = 1)
= I(k) + Sum_1_to_N(T(j,k)*V(j))


For d
-
s
-
a
-
1,






Eckt = Enot(Va,Vb) + Eand(Va,Vb,Vc) +
Eor(Va,Vc,Vd)


Initial activation values are 0, that is the
logic values assigned to the signals.


Then randomly perturb nodes to obtain
Eckt = 0

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Sinha: EE7250

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Fast Techniques


Simulated neural networks


gradient
descent, simulated annealing


Neurocomputer
-

ANZA


0
-
1 Quadratic Programming




path sensitization


Transitive closure


implication graph

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Sinha: EE7250

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References


Neural Methods and Algorithms for Digital Testing, Srimat Chakradhar, V.D.
Agrawal, M.L. Bushnell


Toward Massively Parallel Automatic Test Generation.SRIMAT T. HAKRADHAR,
STUDENT MEMBER, IEEE, MICHAEL L. BUSHNELL,


Generalized Hopfield Neural Network for Concurrent Testing Julio Ortega,
Albert0 Prieto,
Member, ZEEE,
Antonio Lloris, and Francisco
J.
Pelayo