EE5900: Layout Optimizations of Robust VLSI Circuits

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Oct 30, 2013 (3 years and 9 months ago)

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EE5900: Layout Optimizations of
Robust VLSI Circuits

Prof. Shiyan Hu

shiyan@mtu.edu

Office: EERC 731

2


Lecture

Hours
:

Tuesday

and

Thursday

9
:
35
am
-
10
:
50
am


Location
:

EERC

226


Instructor
:

Shiyan

Hu


Email
:

shiyan@mtu
.
edu


Office
:

EERC

731


Phone
:

906
-
287
-
2941


Office

Hour
:

Tuesday

and

Thursday

11
:
00
am
-
12
:
00
pm
.


Class

web

page


http
:
//www
.
ece
.
mtu
.
edu/faculty/shiyan/EE
5900
spring
08


Prerequisites


Basic

understanding

of

algorithms


Basic

understanding

of

circuits

Course Logistics

3


Lecture


No textbook is required


Lecture notes will be posted on class web site


Grading policy


Homework: 30%


Midterm Exam: 30%


Project: 40%

Notes

4

Chip

5

Microprocessor

IBM S/390 Microprocessor

0.13um CMOS technology

47 million transistors

1 GHz

6

Cross
-
Section of A Chip

7

ITRS

8

Basic Components In VLSI Circuits


Devices


Transistors


Logic gates and cells


Function blocks


Interconnects


Local interconnects


Global interconnects


Clock interconnects


Power/ground nets

CMOS transistors

3 terminals in CMOS transistors:



G: Gate



D: Drain



S: Source

nMOS transistor/switch


X=1 switch closes (ON)


X=0 switch opens (OFF)


pMOS transistor/switch


X=1 switch opens (OFF)


X=0 switch closes (ON)


CMOS Inverter

X

F =
X’

Logic symbol

X

F =
X’

+Vdd

GRD

Transistor
-
level schematic

Operation:



X=1


nMOS switch conducts (pMOS is open)


and draws from GRD


F=0



X=0


pMOS switch conducts (nMOST is open)


and draws from +Vdd


F=1

11

System

Specification

Chip

Manual

Automation



Large number of devices



Optimization requirements for high performance



Time
-
to
-
market competition



Power (and other) constraints

Chip Design

12

Time
-
To
-
Market

13

Design Automation


Use automation tools (software/algorithm) to
design large
-
scale circuits


Circuit


Optimization


Industry


IBM, Intel, AMD, Cadence, Synopsys, TI, Magma,
Mentor Graphics,
Freescale




More than half of companies in Silicon Valley are
hardware
-
related


New challenges in
nanoscale

circuits

14

Economic Impact

Semiconductor industry has been one of the fastest growing
sectors of worldwide economy.

15

System Specification

Functional Design

Logic Design and
Synthesis

e.g., Verilog

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))

VLSI Design Cycle

16

Physical (Layout)
Design

Fabrication

Packaging

VLSI Design Cycle (cont.)

17

Physical

design

flow

link


Given

a

circuit

after

logic

synthesis,

to

convert

it

into

a

layout

(i
.
e
.
,

determine

the

physical

location

of

each

gate

and

the

interconnects

between

gates)
.

Physical Design

PD

Better delay, better wirelength…

18

Nanometer Challenges


Interconnect
-
limited designs


Interconnect performance limitation


Interconnect modeling complexity


Interconnect reliability (signal integrity)


Power barrier (esp. leakage)


Variation effects


High degree of on
-
chip integration


Complexity and productivity


System on a chip

19

Moore’s Law


The minimum transistor feature size decreases by
0.7X every three years (Electronics Magazine, Vol.
38, April 1965)


Consequences of smaller transistors:


Faster transistor switching


More transistors per chip


True in the past 40 years!


Not true now


Interconnects


Variations


Need more powerful CAD tools

20

Source:

Gordon Moore, Chairman Emeritus, Intel Corp.

0

50

100

150

200

250

300

Technology generation (

m
)

Delay (psec)

Transistor/Gate delay

Interconnect delay

0.8

0.5

0.25

0.35

Interconnects Dominate

21

Transistors/Cells

Interconnection

Interconnection

Transistors/Cells

Conventional Approach

New Approach

Interconnect
-
Driven Design

New Paradigm for VLSI Design

22

Power Crisis


Exponential increase in sub
-
threshold leakage presents
one of the most challenging issues in sub
-
90nm
technologies.

(courtesy of IBM)

23

Power density

4004

8008

8080

8085

8086

286

386

486

Pentium
®

proc

P6

1

10

100

1000

10000

1970

1980

1990

2000

2010

Year

Power Density (W/cm2)

Hot Plate

Nuclear

Reactor

Rocket

Nozzle

Courtesy, Intel

24

Robust Design For Variations


Variations


The difference between the designed value and the actual
value


Robust design


Mitigate or compensate for variations


Robustness for lithography
-
induced variations

25

25

Chip Design and Fabrication

Lithography Process

Designed Chip Layout

Fabricated Chip

26

26

Photo
-
Lithography Process

oxidation

optical

mask

process

step

photoresist coating

photoresist

removal (ashing)

spin, rinse, dry

acid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).

Part of layout

27

27

Lithography System

Illumination

Mask

Objective Lens

Aperture

Wafer

193
nm
wavelength

45
nm

features

28

28

Mask v.s. Printing

0.25µ

0.18µ

0.13µ

90
-
nm

65
-
nm

Layout

What you
design is
NOT what
you get!

29

29

Motivation


Chip design cannot be fabricated


Gap


Lithography technology: 193nm wavelength


VLSI technology: 45nm features


Lithography induced variations


Impact on timing and power


Even for 180nm technology, variations up to 20x in
leakage power and 30% in frequency were reported.


Technology node

130nm

90nm

65nm

45nm

Gate length (nm)

Tolerable variation (nm)

90

5.3

53

3.75

35

2.5

28

2

Wavelength (nm)

248

193

193

193

30

30

Gap: Lithography Tech. v.s. VLSI Tech.

193
nm

28
nm, tolerable
distortion: 2nm

Increasing gap


Printability problem (and
thus variations) more
severe!

31

Topics


Traditional VLSI physical design flow


Interconnect optimizations and algorithms


Placement


Low power


Variation
-
aware flow


Statistical optimizations


Design for manufacturability


Optimization techniques


Industrial flows

32

VLSI CAD Conferences


DAC


Design Automation Conference


ICCAD


International Conference on Computer
-
Aided
Design


ISPD


International Symposium on Physical Design


ASP
-
DAC


Asia and South Pacific DAC


DATE


Design Automation and Test in Europe

33

VLSI CAD Journals


IEEE TCAD


IEEE Transactions on CAD of Integrated Circuits
and Systems


IEEE TVLSI


IEEE Transactions on VLSI Systems


ACM TODAES


ACM Transactions on Design Automation of
Electronic Systems


IEEE TCAS


IEEE Transactions on Circuits and Systems


Integration, the VLSI Journal