Chapter 1: Introduction to 68HC11

canolaokahumpkaElectronics - Devices

Nov 2, 2013 (3 years and 11 months ago)

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The 68HC11 Microcontroller

Chapter 1: Introduction to 68HC11

The 68HC11 Microcontroller

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The 68HC11 Microcontroller

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The 68HC11 Microcontroller

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The 68HC11 Microcontroller

Memory Addressing


Memory consists of addressable locations

A memory location has 2 components: address and contents

Data transfer between CPU and memory involves address

bus and data bus

CPU

memory

address bus lines

data bus lines

Figure 1.5 Data transfer between CPU and memory

address

contents

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The 68HC11 Microcontroller

68HC11 addressing modes

Table 1.1 Prefix for number representation

Base

Prefix

binary

octal

decimal

hexadecimal

%

@

nothing*

$

*Note: Some assemblers use &

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The 68HC11 Microcontroller

ADDRESSING
MODES

Operands needed in an instruction are specified by one of the 6

addressing modes

Immediate mode

Direct mode

Extended mode

Indexed mode

Inherent mode

Relative mode

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The 68HC11 Microcontroller

Immediate mode

The actual operand is contained in the byte or bytes immediately following the

instruction opcode



LDAA #22


ADDA #@32


LDD #1000


Note that the (#) is a critical assembler directive!

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The 68HC11 Microcontroller

Direct mode

A one
-
byte value is used as the address of a memory operand (located in on
-
chip SRAM)



ADDA $10


SUBA $20


LDD $30

Extended mode


A two
-
byte value is used as the address of a memory operand



LDAA $1000


LDX $1000


ADDD $1030

Indexed mode


The sum of one of the index registers and an 8
-
bit value is used as the address of a

memory operand



ADDA 10,X


LDAA 3,Y


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The 68HC11 Microcontroller

Inherent mode


-

Operands are implied by the instruction

-

No address information is needed




ABA



INCB



INX


Relative mode


-

Used in branch instructions to specify the branch target

-

Specified using either a 16
-
bit value or a label (preferred)




...



BEQ there



ADDA #10



...

there

DECB

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The 68HC11 Microcontroller

A Sample of 68HC11 Instructions

The LOAD instructions


A group of instructions that place a value or copy the contents of a memory

location (or locations) into a register



LDAA

<opr> Load Accumulator A


LDAB

<opr> Load Accumulator B


LDD

<opr> Load Double Accumulator D


LDX

<opr> Load Index Register X


LDY

<opr> Load Index Register Y


LDS

<opr> Load Stack Pointer




<opr>
can be
immediate
,
direct
,
extended
, or
index mode



Examples



LDAA

$10


LDX

#$1000

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The 68HC11 Microcontroller

The ADD instruction


A group of instructions perform addition operation



ABA


ABX


ABY


ADDA <opr>


ADDB <opr>


ADDD <opr>


ADCA <opr>


ADCB <opr>



<opr> is specified using
immediate, direct, extended
, or
index mode


Examples
.



ADDA #10


ADDA $20


ADDD $30

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The 68HC11 Microcontroller

The SUB instruction


A group of instructions that perform the subtract operation



SBA


SUBA

<opr>


SUBB

<opr>


SUBD

<opr>


SBCA

<opr>

; A


[A]
-

<opr>
-

C flag


SBCB

<opr>

; A


[B]
-

<opr>
-

C flag




<opr> can be immediate, direct, extended, or index mode

Examples



SUBA

#10


SUBA

$10


SUBA

0,X


SUBD

10,X

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The 68HC11 Microcontroller

The STORE instruction

A group of instructions that store the contents of a register into

a memory location or memory locations



STAA

<addr>


STAB

<addr>


STD

<addr>


STX

<addr>


STY

<addr>


STS

<addr>




<addr>
can be
direct
,
extended
, or
index

mode


Examples
:



STAA

$20


STAA

10,X


STD

$10


STD

$1000


STD

0,X

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The 68HC11 Microcontroller

The

68HC11 Machine Code


A 68HC11

instruction consists of 1 to 2 bytes of opcode and 0 to 3 bytes of

operand information


Examples





Machine instructions

Assembly instruction



(in hex format)



LDAA #29


86 1D


STAA $00

97 00


ADDA $02

9B 02


STAA $01

97 01


INY



18 08



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The 68HC11 Microcontroller

Decoding

machine language instructions

Procedure


Step 1


Compare the first one or two bytes with the opcode table to identify the



corresponding assembly mnemonic and format.

Step 2


Identify the operand bytes after the opcode field.

Step 3


Write down the corresponding assembly instruction.

Step 4


Repeat step 1 to 3 until the machine code file is exhausted.


A sample of machine codes and assembly instruction format


machine code assembly instruction format



01



NOP


86



LDAA IMM


96



LDAA DIR


C6



LDAB IMM


D6



LDAB DIR


CC



LDD IMM


DC



LDD DIR


8B



ADDA IMM


9B



ADDA DIR


CB



ADDB IMM

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The 68HC11 Microcontroller

DB


ADDB DIR

C3


ADDD IMM

D3


ADDD DIR

97


STAA DIR

D7


STAB DIR

DD


STD DIR

machine code

assembly instruction format

Example
. Disassemble the following machine code to its corresponding assembly


instructions.



96 30 8B 07 97 30 96 31

Solution
:

The disassembly process starts from the leftmost byte. We next look up

the machine code table to see which instruction it corresponds to.


Instruction 1.

Step 1. The first byte 96 corresponds to the instruction LDAA DIR.

Step 2. The second byte, 30, is the direct address.

Step 3. Therefore, the first instruction is LDAA $30.

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The 68HC11 Microcontroller

Instruction 2
.

Step 1. The third byte (8B) corresponds to the instruction ADDA IMM.

Step 2. The immediate value is 07.

Step 3. Therefore, the second instruction is ADDA $07.


Instruction 3
.

Step 1. The fifth byte (97) corresponds to the instruction STAA DIR.

Step 2. The DIR address is the next byte 30.

Step 3. Therefore, the third instruction is STAA $30.


Instruction 4
.

Step 1. The seventh byte (96) corresponds to the instruction LDAA DIR.

Step 2. The DIR value is the next byte 31.

Step 3. Therefore, the four instruction is LDAA $31.

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The 68HC11 Microcontroller

machine code assembly instruction format




01

NOP



86

LDAA IMM



96

LDAA DIR



C6

LDAB IMM



D6

LDAB DIR



CC

LDD IMM



DC

LDD DIR



8B

ADDA IMM



9B

ADDA DIR



CB

ADDB IMM


DB

ADDB DIR


C3

ADDD IMM


D3

ADDD DIR


97

STAA DIR


D7

STAB DIR


DD

STD DIR



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The 68HC11 Microcontroller

The 68HC11 Instruction Execution Cycle


-


Perform a sequence of read cycles to fetch instruction opcode byte and address



information.

-


Optionally perform read cycle(s) required to fetch the memory operand.

-

Perform the operation specified by the opcode.

-

Optionally write back the result to a register or a memory location.


-

Consider the following 3 instructions



Assembly instruction

Memory location

Opcode






LDAA $2000

$C000

B6 20 00


ADAA $3000

$C003

BB 30 00


STAA $2000

$C006

B7 20 00

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The 68HC11 Microcontroller

Instruction
LDAA $2000


Step 1.
Place the value in PC on the address bus with a request to read the contents of that


location.

Step 2.
The opcode byte
$B6
at $C000 is returned to the CPU and PC is incremented by 1.

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The 68HC11 Microcontroller

Step 3.
CPU performs two read cycles to obtain the extended address $2000 from locations


$C001 and $C002. At the end the value of PC is incremented to $C003

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The 68HC11 Microcontroller

Figure 1.12 Instruction 1
--
execution read cycle

Memory contents

$19

$37

CPU

.

.

.

$2000

Address bus

Data bus

$19

$2000

Address

$3000

Step 4. The CPU performs another read to get the contents of the memory location at


$2000, which is $19. The value $19 will be loaded into accumulator A.