Presentation Part A

FINAL PRESENTATION

Saleem Sabbagh & Najeeb Darawshy

Supervisors: Mony Orbach, Technion &



Ilia Averbouch, IBM

FPGA Based SAT Solver

Started at: Winter 2012

Duration: Semester

OUTLINE


What is SAT


Reminder
-

description and goals


Flow diagram


Circuit diagram


Example simulation results


Live Presentation


Runtimes


Compilation times


Notes & Conclusions


What’s Next

WHAT IS SAT


Boolean Satisfiability Problem


Given a Boolean propositional formula, does
there
exist assignment
of values such that the
formula becomes true
?


e.g., given the formula


f=(x
1
˅

x
3

˅

-
x
4
)
˄

(
x
4
)

˄

(x
2
˅

-
x
3
)


are there values of x
1
,x
2
,x
3
,x
4
that

produce f=‘
1
’

REMINDER
–

DESCRIPTION AND GOALS


Description:


Hardware based SAT Solver


Goals:


Implementing SAT instances into FPGA


Measuring build and run times for benchmark
examples


Enabling
further development of fast hardware
based SAT Solver



FLOW DIAGRAM

Conversion

Synthesis

Device

Programmer

Running

SAT Solver

CIRCUIT DIAGRAM

clk

en

F

sOUT

timeOUT

CIRCUIT DIAGRAM
-

LFSR


LFSR Random Generator (Generic width up to
168
bits)



CIRCUIT DIAGRAM
-

SMARTSHIFT


A right shift
register with Parallel
Load, Shift Enable, Parallel
and Serial output


While SAT still unsatisfiable F=0, NOT(F)=1 therefor:


LOAD=1


D is loaded into register;


SE=0


Shift not enabled.


When found satisfying input F=1, NOT(F)=0 therefor:


LOAD=0


Stop Loading Parallel input;


SE=1


Start shifting;


MSB


Satisfying input.



EXAMPLE SIMULATION RESULTS


For SAT instance of
20
variables and
91
clauses







Satisfying input:
00101011011101000000

RUNTIME

*
Clock frequency is
50
M [Hz]


0.0011776

0.0340384

21.36

35.588

4277.75

0
500
1000
1500
2000
2500
3000
3500
4000
4500
20
25
30
35
40
Run Time [sec]

# Variables

RunTime Vs. #Variables

COMPILATION TIMES

*
Clock frequency is 50M [Hz]


17.6

15.2

22.5

22.75

19.333

18.4

19.25

19.25

20

22

24.75

30

29.5

59

413.2

4729.4

0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
Average Compilation Time [sec]

# Variables

Compilation Time Vs. #Variables

COMPILATION TIMES
-

ANALYSIS


Compilation time is comprised of two main stages, Analysis &
Synthesis and Place & Route. We found the problem to be
associated directly to the peak interconnect usage during Place
& Route stage.



9.25

12.5

21.75

24.5

27

29

39.75

77.8

87.4

93.75

0
20
40
60
80
100
75
100
125
150
175
200
225
500
750
1000
Peak Interconnect Usage [%]

# Variables

Peak Interconnect Usage Vs. #Variables

NOTES


Tried several solutions for
1000
-
variables SAT with
4250
clauses in order to decrease compilation time:


Low Priority Optimization during Compliation
–

Did not help.


Better Altera board, Altera Stratix V
–

85
% cut in compilation time.


In order to better sample our variables spectrum, We have used
two applications:


Java based Random SAT generator with
4.25
:
1
ratio (
Clauses:Variables
) which was used
for compilation time analysis.


Cpp based satisfyable/unsatisfyable SAT generator used in official sat competitions which
was used for runtimes analysis.

WHATS NEXT


Two approaches


Improving runtimes by designing smart sat solver
instead of inefficient LFSR random generator


Improving compilation times by:


Understanding Altera compilation algorithms to enable
faster SAT
-
specific fpga ready files.


Smart use of memory on FPGA to implement SAT.


Thank you!


Questions?