MOSFET DC Circuits Analysis

1.

Assume an operation region (usually the saturation region)

2.

Apply KVL at the gate source loop to find

V

GS

3.

Use

V

GS

from step 2 to calculate

I

D

4.

Apply KVL at the drain source loop and use

I

D

from step 3 to find

V

DS

5.

Check the validity of operation region assumptions by comparing

V

DS

to

V

DSat

6.

Change assumptions and analyze again if required.

NOTES :

An enhancement-mode device with

V

DS

=

V

GS

is always in saturation

If we have a source resistance, we need to solve the equations in steps 2

and 3 together to find ID and VGS.

If we include channel length modulation or we are in the triode region, we

will solve the equations in steps 3 and 4 together

If we include channel length modulation or we are in the triode region and

we have a source resistance, we will solve the equations in steps 2, 3, and 4

together

Bias Analysis: Example 1

Problem:Find the Q-pt (

I

D

, V

DS

)

Given:

V

TN

=1V,

K

n

=25μA/V2

Approach:Assume operation

region, find Q-point, check to see

if result is consistent with

operation region

Assumption:Transistor is

saturated,

I

G

=I

B

=0

Analysis: First, simplify circuit,

split

V

DD

into two equal-valued

sources and apply Thevenin

transformation to find

V

EQ

and

R

EQ

for gate-bias voltage

Bias Analysis: Example 1 (contd.)

S

R

D

I

GS

V

EQ

V

+

=

KVL at G-S loop,

2

2

K

n

IVV

GSTN

D

⎛⎞

⎜⎟

⎝⎠

=−

63

25103910

2

41

2

VV

GS

GS

⎛⎞⎛⎞

⎜⎟⎜⎟

⎜⎟⎜⎟

⎛⎞

⎝⎠⎝⎠

⎜⎟

⎝⎠

−

××

=

+−

021.705.0

2

=−+

GS

V

GS

V

V66.2,V71.2

+

−

=

∴

GS

V

Since

V

GS

<V

TN

for

V

GS

= -2.71 V

and MOSFET will be cut-off,

we ignore it

V66.2

+

=

GS

V

and

I

D

= 34.4μA

DS

V

S

R

D

R

D

I

DD

V

+

+

=)(

V08.6

=

∴

DS

V

VDS>VGS-VTN. Hence saturation

region assumption is correct.

Q-pt: (34.4μA, 6.08 V)

with

V

GS

= 2.66 V

2

2

KR

nS

VVVV

GSTN

EQGS

⎛⎞

⎜⎟

⎝⎠

∴

=+−

KVL at D-S loop,

Bias Analysis: Example 2

Estimate value of

I

D

and use

it to find

V

GS

and

V

SB

Use

V

SB

to calculate

V

TN

Find

I

D

’

using above 2 steps

If

I

D

’

is not same as original

I

D

estimate, start again.

Find the Q-point for the shown

circuit with body effect using

2φF=0.6 V, VTO=1V, and γ=0.5V1/2:

D

I

S

R

D

I

EQ

V

GS

V

000,226

−

=

−

=

D

I

S

R

D

I

SB

V

000,22

=

=

)22(

FF

SB

V

TO

V

TN

V

φφγ

−++=

)6.06.0(5.01

−

+

+

=

∴

SB

V

TN

V

2

2

6

1025

'

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

−

−

×

=

TN

V

GS

V

D

I

Iterative solution can be found

by following steps:

KVL at G-S loop,

Bias Analysis: Example 2 (contd.)

The iteration sequence leads to

I

D

= 88.0 μA

V48.6000,4010)(

=

−

=

+

−

=

D

I

S

R

D

R

D

I

DD

V

DS

V

V

DS

>V

GS

-V

TN

. Hence saturation region assumption is correct.

Q-pt: (88.0μA, 6.48 V)

Bias Analysis: Example 3

Assumption:

I

G

=I

B

=0, transistor

is saturated (since

V

DS

=

V

GS

)

Analysis:

VVVIR

DDDD

DSGS

==−

2

2

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

−−=

TN

V

GS

V

D

R

n

K

DD

V

GS

V

2

1

2

4

10

4

106.2

3.3

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

−

−

×

−=

∴

GS

V

GS

V

V00.2,V769.0

+

−

=

∴

GS

V

Since

V

GS

<V

TN

for

V

GS

=

-0.769

V and MOSFET will be cut-off,

it will be ignored.

V00.2

+

=

GS

V

and

I

D

= 130μA

V

DS

>V

GS

-V

TN

. Hence saturation

region assumption is correct.

Q-pt: (130μA, 2.00 V)

Find the Q-point for the shown circuit?

Bias Analysis: Example 4

( Biasing in Triode Region)

Assumption:

I

G

=I

B

=0,

transistor is saturated

Analysis:

V

GS

=V

DD

=

4 V

mA13.1

2

)14(

2

V

μA

2

250

=−=

D

I

VIRV

DDDD

DS

=

+

V19.2

=

∴

DS

V

But

V

DS

<V

GS

-V

TN

. Hence, saturation

region assumption is incorrect Using

triode region equation,

DS

V

D

I

+

=

∴

16004

DS

V

DS

V

DS

V)

2

14(

2

V

μA

250*16004−−=−

V3.2=

∴

DS

V

and

I

D

=1.06 mA

V

DS

<V

GS

-V

TN

, transistor is in triode region

Q-pt:(1.06 mA, 2.3 V)

Find the Q-point for the shown circuit?

KVL at D-S loop,

Bias Analysis: Example 5

Assumption:

I

G

=

I

B

=0, transistor

is saturated (since

V

DS

=

V

GS

)

Analysis:

15V(220kΩ)0IV

SG

D

−−=

2

μA

50

15V(220kΩ)20

22

V

VV

SG

SG

⎛⎞

⎜⎟

⎝⎠

∴

−−−=

V45.3,V369.0=

∴

SG

V

Since

V

SG

= 0.369 V is less than

|VTP|= 2 V, ∴

V

SG

= 3.45 V

I

D

= 52.5μAand

V

SG

= 3.45 V

Hence saturation assumption is correct.

Q-pt: (52.5μA, 3.45 V)

TP

V

SG

V

SD

V−>

Find the Q-point for the shown circuit?

KVL at G-S loop,

MOSFET Circuits At DC

Example 6: Design the circuit of Fig. Ex6 so that the transistoroperates at

I

D

=0.3 mAand

V

D

=+1V. The NMOS transistor has

V

t

= 1V,

μ

n

C

ox

=20 μA/V2,

L

=1 μm, and

W

=30μm.

Example 7: Design the circuit in Fig. Ex7 to obtain a current

I

D

of 0.4 mA. Find

the value required for

R

and find the DC voltage

V

D

. The NMOS transistor has

V

t

= 0.5V,

μ

n

C

ox

=20 μA/V2,

L

=1 μm, and

W

=40μm.

Example 8: Design the circuit in Fig. Ex8 to establish a drain voltage of 0.1 V.

What is the effective resistance between drain and source at this operating

point? Let

V

t

= 1V and

k

n

= 1 mA/V2

Fig. Ex6

Fig. Ex8

Fig. Ex7

MOSFET Circuits At DC (contd.)

Example 9: Analyze the circuit shown in Fig. Ex9 to determine

the voltages at all nodes and the currents through all branches.

Let

V

t

= 1V and

k

n

’

(W/L)

= 1 mA/V2

Example 10: Design the circuit in Fig. Ex10 for the shown

currents and voltages (i.efind R, (W/L) for each transistor). Let

Vt=1 V,

μ

n

C

ox

=20 μA/V2

Fig. Ex9

Fig. Ex10

MOSFET As A Current Source

Ideal current source

gives fixed output

current regardless of

the voltage across it.

MOSFET behaves as

as an ideal current

source if biased in

the pinch-off region

(output current

depends on terminal

voltage).

NMOS Current Mirror

Assumption:

M

1

and

M

2

have identical

V

TN

,

K

n

’

,

λ

and

W/L

and are

in saturation.

1

'

2

1

2

M

K

W

n

IVVV

REFTN

GS1

DS1

L

λ

⎛⎞

⎛⎞

⎛⎞

⎜⎟

⎜⎟

⎜⎟

⎜⎟

⎝⎠

⎝⎠

⎜⎟

⎝⎠

=−+

2

'

2

1

2

M

K

W

n

IVVV

TN

OGS2

DS2

L

λ

⎛⎞

⎛⎞

⎛⎞

⎜⎟

⎜⎟

⎜⎟

⎜⎟

⎝⎠

⎝⎠

⎜⎟

⎝⎠

=−+

But

V

GS2

=V

GS1

22

11

1

1

MM

MM

WW

V

LL

DS2

III

O

REFREF

WW

V

DS1

LL

λ

λ

⎛⎞

⎜⎟

⎝⎠

⎛⎞

⎜⎟

⎝⎠

⎛⎞⎛⎞

⎜⎟⎜⎟

+

⎝⎠⎝⎠

∴

=≅

⎛⎞⎛⎞

+

⎜⎟⎜⎟

⎝⎠⎝⎠

Thus, output current mirrors

reference current if

V

DS1

=V

DS2

or

λ

=

0, and both transistors have

the same (W/L)

NMOS Current Mirror: Example 11

Find the output current and the minimum output

voltage

v

o

to maintain the given current mirror in

proper operation.

Given data:

I

REF

= 50 μA

, V

O

= 12 V,

V

TN

= 1 V

, K

n

’

= 75 μA/V2,

λ

= 0 V-1,

(W/L)M1

= 2, (W/L)M2=10

Analysis:

2

2(50μA)

1V1.82

μA

2*75

(1)

2

1

V

I

REF

VVV

TN

GS

W

KV

n

DS

L

λ

⎛⎞

′

⎜⎟

⎜⎟

⎜⎟

⎝⎠

=+=+=

+

Hence,

V

omin

=VGS

–V

TN

= 0.82 V.

μA250

1

2

==

∴

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

M

L

W

M

L

W

REF

I

O

I

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