Digital Integrated Circuits Lecture 4: DC & Transient Response

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Oct 7, 2013 (4 years and 1 month ago)

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Digital Integrated Circuits
Lecture 4: DC & Transient
Response
Chih-Wei Liu
VLSI Signal Processing LAB
National ChiaoTung University
cwliu@twins.ee.nctu.edu.tw
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Outline

Pass Transistors

DC Response

Logic Levels and Noise Margins

Transient Response

RC Delay Models

Delay Estimation
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Activity
1)If the width of a transistor increases, the current will
increasedecreasenot change
2)If the length of a transistor increases, the current will
increasedecreasenot change
3)If the supply voltage of a chip increases, the maximum transistor
current will
increasedecreasenot change
4)If the width of a transistor increases, its gate capacitance will
increasedecreasenot change
5)If the length of a transistor increases, its gate capacitance will
increasedecreasenot change
6)If the supply voltage of a chip increases, the gate capacitance of
each transistor will
increasedecreasenot change
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Activity
1)If the width of a transistor increases, the current will
increasedecreasenot change
2)If the length of a transistor increases, the current will
increasedecreasenot change
3)If the supply voltage of a chip increases, the maximum transistor
current will
increasedecreasenot change
4)If the width of a transistor increases, its gate capacitance will
increasedecreasenot change
5)If the length of a transistor increases, its gate capacitance will
increasedecreasenot change
6)If the supply voltage of a chip increases, the gate capacitance of
each transistor will
increasedecreasenot change
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Pass Transistors

We have assumed source is grounded

What if source > 0?

e.g. pass transistor passing VDD
VDD
VDD
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Pass Transistors

We have assumed source is grounded

What if source > 0?

e.g. pass transistor passing VDD

Vg
= VDD

If Vs
> VDD-Vt, Vgs
< Vt

Hence transistor would turn itself off

nMOS pass transistors pull no higher than VDD-Vtn

Called a degraded “1”

Approach degraded value slowly (low I
ds)

pMOS pass transistors pull no lower than V
tp

Transmission gates are needed to pass both 0 and 1
VDD
VDD
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Pass Transistor Ckts
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
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Pass Transistor Ckts
V
DD
V
DD
V
s
= V
DD-Vtn
V
SS
V
s
= |V
tp|
V
DD
V
DD-Vtn
V
DD-V
tn
V
DD-V
tn
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD-V
tn
V
DD-2V
tn
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DC Response

DC Response: Vout
vs. Vin
for a gate

Ex: Inverter

When Vin
= 0 -> V
out
= VDD

When Vin
= VDD
-> V
out
= 0

In between, Vout
depends on
transistor size and current

By KCL, must settle such that
Idsn
= |Idsp|

We could solve equations

But graphical solution gives more insight
Idsn
Idsp
Vout
VDD
Vin
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Transistor Operation

Current depends on region of transistor behavior

For what Vin
and Vout
are nMOS and pMOS in

Cutoff?

Linear?

Saturation?
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nMOS Operation
Vgsn
> Vtn
Vdsn
> Vgsn
–V
tn
Vgsn
> Vtn
Vdsn
< Vgsn
–V
tn
Vgsn
< Vtn
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
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nMOS Operation
Vgsn
> Vtn
Vdsn
> Vgsn
–V
tn
Vgsn
> Vtn
Vdsn
< Vgsn
–V
tn
Vgsn
< Vtn
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
Vgsn
= Vin
Vdsn
= Vout
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nMOS Operation
Vgsn
> Vtn
Vin
> Vtn
Vdsn
> Vgsn
–V
tn
Vout
> Vin
-V
tn
Vgsn
> Vtn
Vin
> Vtn
Vdsn
< Vgsn
–V
tn
Vout
< Vin
-V
tn
Vgsn
< Vtn
Vin
< Vtn
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
Vgsn
= Vin
Vdsn
= Vout
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pMOS Operation
Vgsp
<
Vdsp
<
Vgsp
<
Vdsp
>
Vgsp
>
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
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pMOS Operation
Vgsp
< Vtp
Vdsp
< Vgsp
–V
tp
Vgsp
< Vtp
Vdsp
> Vgsp
–V
tp
Vgsp
> Vtp
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
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pMOS Operation
Vgsp
< Vtp
Vdsp
< Vgsp
–V
tp
Vgsp
< Vtp
Vdsp
> Vgsp
–V
tp
Vgsp
> Vtp
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
Vgsp
= Vin
-V
DD
Vdsp
= Vout
-V
DD
Vtp
< 0
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pMOS Operation
Vgsp
< Vtp
Vin
< VDD
+ Vtp
Vdsp
< Vgsp
–V
tp
Vout
< Vin
-V
tp
Vgsp
< Vtp
Vin
< VDD
+ Vtp
Vdsp
> Vgsp
–V
tp
Vout
> Vin
-V
tp
Vgsp
> Vtp
Vin
> VDD
+ Vtp
SaturatedLinearCutoff
Idsn
Idsp
Vout
VDD
Vin
Vgsp
= Vin
-V
DD
Vdsp
= Vout
-V
DD
Vtp
< 0
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I-V Characteristics

Make pMOS is wider than nMOS such that βn
= βp
Vgsn5
Vgsn4
Vgsn3
Vgsn2
Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
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Current vs. V
out, Vin
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |I
dsp
|
Vout
VDD
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Load Line Analysis
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn, |I
dsp
|
Vout
VDD

For a given Vin:

Plot Idsn, Idsp
vs. Vout

Vout
must be where |currents| are equal in
Idsn
Idsp
Vout
VDD
Vin
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Load Line Analysis
Vin0
Vin0
Idsn
, |I
dsp
|
Vout
VDD

Vin
= 0
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Load Line Analysis
Vin1
Vin1
Idsn
, |I
dsp
|
Vout
VDD

Vin
= 0.2VDD
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Load Line Analysis
Vin2
Vin2
Idsn
, |I
dsp
|
Vout
VDD

Vin
= 0.4VDD
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Load Line Analysis
Vin3
Vin3
Idsn
, |I
dsp
|
Vout
VDD

Vin
= 0.6VDD
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Load Line Analysis
Vin4
Vin4
Idsn
, |I
dsp
|
Vout
VDD

Vin
= 0.8VDD
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Load Line Analysis
Vin5
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |I
dsp
|
Vout
VDD

Vin
= VDD
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Load Line Summary
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD
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DC Transfer Curve

Transcribe points onto V
in
vs. Vout
plot
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Vout
VDD
C
V
out
0
Vin
VDD
VDD
AB
D
E
Vtn
V
DD/2V
DD+Vtp
Vin0
Vin1
Vin2
Vin3
Vin4
Vin5
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Operating Regions

Revisit transistor operating regions
C
V
out
0
Vin
VDD
VDD
AB
D
E
Vtn
V
DD/2V
DD+Vtp
E
D
C
B
A
pMOSnMOSRegion
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Operating Regions

Revisit transistor operating regions
C
V
out
0
Vin
VDD
VDD
AB
D
E
Vtn
V
DD/2V
DD+Vtp
CutoffLinearE
SaturationLinearD
SaturationSaturationC
LinearSaturationB
LinearCutoffA
pMOSnMOSRegion
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Beta Ratio

If βp
/ βn
≠1, switching point will move from VDD/2

Called skewedgate

Other gates: collapse into equivalent inverter
Vout
0
Vin
V
DD
VDD
0.5
1
2
10
p
n
β
β
=
0.1
p
n
β
β
=
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Noise Margins

How much noise can a gate input see before it does not
recognize the input?
Indeterminate
Region
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
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Logic Levels

To maximize noise margins, select logic levels at
VDD
Vin
Vout
VDD
βp/βn
> 1
Vin
Vout
0
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Logic Levels

To maximize noise margins, select logic levels at

unity gain point of DC transfer characteristic
VDD
Vin
Vout
VOH
VDD
VOL
VIL
VIH
Vtn
Unity Gain Points
Slope = -1
VDD-
|Vtp|
βp/βn
> 1
Vin
Vout
0
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Transient Response

DC analysistells us Vout
if Vin
is constant

Transient analysistells us Vout(t) if Vin
(t) changes

Requires solving differential equations

Input is usually considered to be a step or ramp

From 0 to VDD or vice versa
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Inverter Step Response

Ex: find step response of inverter driving load cap
0
()
(
)
)
(
o
i
ut
n
out
Vtt
t
V
t
V
d
d
t
=
<
=
=
Vin(t)
Vout(t)
Cload
Idsn
(t)
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Inverter Step Response

Ex: find step response of inverter driving load cap
0
0
()
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
utsn
V
V
uttV
tt
Vt
V
d
dtC
t
It
=−
=
=−
<
()
0
2
2
0
2
)
)
(
()
(
D
DDDt
DD
out
out
outout
D
t
n
t
ds
D
IV
tt
VVVV
VVVVV
t
Vt
Vt
β
β




=
−>−


⎛⎞
−−<−

⎜⎟
⎝⎠

Vin(t)
Vout(t)
Cload
Idsn
(t)
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Inverter Step Response

Ex: find step response of inverter driving load cap
0
0
()
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
utsn
V
V
uttV
tt
Vt
V
d
dtC
t
It
=−
=
=−
<
()
0
2
2
0
2
)
)
(
()
(
D
DDDt
DD
out
out
outout
D
t
n
t
ds
D
IV
tt
VVVV
VVVVV
t
Vt
Vt
β
β




=
−>−


⎛⎞
−−<−

⎜⎟
⎝⎠

Vout
(t)
Vin(t)
t0
t
Vin(t)
Vout(t)
Cload
Idsn
(t)
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Delay Definitions

tpdr: rising propagation delay

From input to rising output crossing VDD/2

tpdf: falling propagation delay

From input to falling output crossing VDD/2

tpd: average propagation delay

tpd
= (tpdr
+ tpdf)/2

tr: rise time

From output crossing 0.2 VDD
to 0.8 VDD

tf: fall time

From output crossing 0.8 VDD
to 0.2 VDD
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Delay Definitions

tcdr: rising contamination delay

From input to rising output crossing VDD/2

tcdf: falling contamination delay

From input to falling output crossing VDD/2

tcd: average contamination delay

tpd
= (tcdr
+ tcdf)/2
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Simulated Inverter Delay

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically

Uses more accurate I-V models too!

But simulations take time to write, may hide insight
(V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0200p400p600p800p1n
tpdf = 66pst
pdr
= 83ps
Vin
Vout
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Delay Estimation

We would like to be able to easily estimate delay

Not as accurate as simulation

But easier to ask “What if?”

The step response usually looks like a 1st
order RC response
with a decaying exponential.

Use RC delay models to estimate delay

C = total capacitance on output node

Use effective resistanceR

So that tpd
= RC

Characterize transistors by finding their effective R

Depends on average current as gate switches
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Effective Resistance

Shockley models have limited value

Not accurate enough for modern transistors

Too complicated for much hand analysis

Simplification: treat transistor as resistor

Replace Ids(Vds, Vgs) with effective resistance R

Ids
= Vds/R

R averaged across switching of digital gate

Too inaccurate to predict current at any given time

But good enough to predict RC delay