Analytical Solutions for Heat

Analytical Solutions for Heat
Flow in IC Interconnects

Kuntal Bhattacharyya

Project Synopsis


Project '03

Kuntal Bhattacharyya

2

Topics Covered

•
Failures in Interconnects

•
Reliability Concepts

•
Interconnect Thermal Profile

•
Hot Spots and Via Effects

•
Thermal Resistance in Interconnects

•
Calculation of Healing Length

•
Static Heat solution in (r,z,fi) plane


Project '03

Kuntal Bhattacharyya

3

Failures in Interconnects
1,2

•
Electromigration

•
“
Current Crowding
”

•
Increase in Joule/Self
Heating

•
Increase in the overall
line temperature


Project '03

Kuntal Bhattacharyya

4

Reliability Measures

•
Electromigration is a temperature dependent
effect. Temperature control is necessary.
This needs efficient Self Heating.

•
Current density is to be kept low. Ensured
by proper Interconnect parameters ( L, R/L,
C/L)

•
To achieve reasonable Interconnect lifetime,
ITRS standards should be maintained.

Project '03

Kuntal Bhattacharyya

5

Interconnect Thermal Profile
3,4,5

Assumptions


•
Though ‘k’ is a function of
temperature and position, it is
assumed to be constant.

•
All four sidewalls are
considered to be adiabatic.

•
Heat is exchanged only through
the underlying substrate.

Project '03

Kuntal Bhattacharyya

6

Interconnect Heat Flow
3

•
Under stated assumptions and steady state conditions, the system of
heat equation is




k[

2
T/

x
2
+

2
T/

y
2
+

2
T/

z
2
]+Q* =0


•
The 1
-
D equation is


2
T/

x
2
=
-
Q*/k
m




The volumetric heat generation rate
Q*
is a factor of

1.
Power generation rate due to RMS current.

2.
Heat loss rate between interconnect and substrate.


•
The summarized interconnect heat flow equations:



d
2

T
line
(x)/dx
2
=

2

T
line
(x)
-


2

T
ref
(x)
-





2
=1/ k
m

[{k
ox
(1+0.88 t
ox
/w)/t
m
t
ox
}
-

I
2
rms


i


⼠
2
t
m
2
]



= I
2
rms


i

/ w
2
t
m
2

k
m


•
Significance of
T
ref





Project '03

Kuntal Bhattacharyya

7

Substrate Thermal Profile
3,5

•
Using the two boundary
conditions T(x=0)= T
ref

and
T(x=L)= T
ref

the interconnect
thermal profile is obtained as




T(x)= (

/

2
)[1
-
{sinh

砫獩sh


⡌
-
x)}/sinh

L崫]
ref




•
Concept of “VIA” and its
importance in heat flow.


Project '03

Kuntal Bhattacharyya

8

Heat Profile Incorporating Via Effect
6

•
Healing length

L
H
=[ (k
M
H t
ILD
/ k
ILD
).(1/s)]
0.5


•
Heat spread factor


s=w
effective
/w



W
effective !!!!!


•
Temperature along wire:

T(x)=

T
0
+



max

[
1
-
{cosh(x/

L
H
)/

cosh(L/

2
L
H
)}]
;




L/
2



x



-
䰯
2



Where


T
max
(=j
2
rms


L
2
H
/ k
M
)


•
Hot spots and vias




Project '03

Kuntal Bhattacharyya

9

Heat profile with test parameters

For the 100nm technological node,

•
W=d=2

m

•
H=t
ILD
=0.8

m


•
k
ILD
=k
SiO2
=1.4W/mK

•
k
M
=k
aluminum
=216.5W/mK

•

M
=

aluminum
=2.65E
-
8

m


•
The length of the interconnect is
the distance between the two ends
of the vias



Therefore, L= 50

m


•
The temperature at different points
on the 50

m length of the
interconnect have been found and
plotted using different values of
“x”, that accounts for the location.
X=0 is the middle of the wire.


Project '03

Kuntal Bhattacharyya

10

Interconnect thermal resistance

•
Rth
e
-
e
=(1/k
M
).L/(w.t)

•
So, the thermal resistance per
unit length:


Rth
e
-
e
/L=1/(k
M.
w.t)= f (w, t)



Project '03

Kuntal Bhattacharyya

11

Chip thermal resistance

Project '03

Kuntal Bhattacharyya

12

Calculation of healing length
6,7

•
Heat flow in devices

•
Should be calculated neglecting
self heating.


•
Comparison between
effects of L
H1
& L
H2


Project '03

Kuntal Bhattacharyya

13

Summary

•
Heat flow equations have been analyzed for an
interconnect, independently, with via
-
effect and
with substrate profile.

•
Thermal resistance of the interconnect and the
chip has been studied. Healing length has been
calculated for given device parameters.

•
Present and future work involves a study of the
static heat conduction equation in the chip in
cylindrical coordinates, and analysis of the
solution.

Project '03

Kuntal Bhattacharyya

14

Bibliography

[1]
Thermal and Electrical Simulation of Deep Submicron Interconnection
Systems
-
R.Streiter, H Wolf, Z Zhu, X Xiao, T Gessner .

[2]

http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm


[3]

K Banerjee, Pedram and Ajami,
Analysis and Optimization of Thermal Issues
in High
-
Performance VLSI
, ISPD’01, April 1
-
4, 2001, Sonoma, California,
USA .

[4]

Ajami, Banerjee, Pedram and Van Ginneken,
Analysis of Non
-
Uniform
Temperature
-
Dependent Interconnect Performance in High Performance
Ics
, DAC’01, June 18
-
22, 2001, Las Vegas, Nevada, USA.

[5]

Ajami, Pedram and Banerjee,
Effects of Non
-
Uniform Substrate Temperature
on the Clock Signal Integrity in High Performance Designs
, CICC 2001.

[6]

Chiang, Banerjee, Saraswat,
A New Analytical Thermal Model For Multilevel
ULSI Interconnects Incorporating Via Effects
, CIS, Stanford University, CA

[7]

J S Brodsky,
Physics
-
based thermal impedance models for the simulation of
self
-
heating in semiconductor devices and circuits
, Dissertation presented to
the University of Florida, 1997.