DDR Memory Interfaces

bloatdecorumSoftware and s/w Development

Oct 30, 2013 (3 years and 10 months ago)

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DDR Memory Interfaces

Double Data Rate (DDR) Memory


Maximize throughput:


High clock rate (133+ MHz)


DDR, 100


200 MHz; DDR2, 200


533
MHz; DDR3: 400


800 MHz


Transfer data on both edges


Burst reads and writes


Short access times


Simple performance definition:


Frequency rate


133 MHz, 166 MHz, etc.


CAS (Column Address Strobe) Latency
(CL), in clock cycles


delay time between when a column access
is requested, and the data is available


High density (capacitor and a few FETs
per bit), but complex interface


requires memory refreshes


reads are destructive


Tabl e 2 from “SDRAM Memory Systems: Archi tecture Overvi ew and Desi gn Veri fi cati on

Synchronous SRAM (NOT DDR) Read Cycle

Accessing Synchronous SRAM fairly straightforward, easy to design, fairly relaxed timing.

From IBM App Note
Understanding Static RAM Operation
, sramop.pdf

DDR2
Simplified

State Diagram

DDR Timing Difficulties


Source synchronous: data and clock from data
source


new clock domain at receiver


Clock at 333 MHz (or faster):


Period: 3 ns


Half Period: 1.5 ns


Routing from IOB to destination delays can easily
vary from < .5 ns to > 2+ ns


a significant portion
of our half
-
period!


IOB placement?


Destination placement?

Double Data Rate to Single Data Rate

From
DDR2 SDRAM Interface for Spartan
-
3 Generation FPGAs
, xapp454.pdf

Clock delays
determined
during
calibration at
startup

General FPGA Memory Interface Architecture

Multi
-
Port

DDR
Interface

Custom
Interface

DDR

Custom
Interface

Custom
Interface

Custom
Interface

FPGA

General FPGA Memory Interface Architecture

Multi
-
Port

DDR
Interface

Custom
Interface

DDR

Custom
Interface

Custom
Interface

Custom
Interface

FPGA

MIG (all Xilinx)

MCB (Spartan 6)

MPMC (PLB) &

Personality Modules

or

AXI & AXI Interfaces

DDR Interface: MIG


Xilinx provides the
M
emory
I
nterface
G
enerator (MIG)


Software tool that takes as inputs…:


Memory definition (speed, CAS, data width, banks, etc.)


FPGA part


Preferred input locations (sides, etc.)


…and produces:


RTL PHY or Memory Controller Block


Pin locations


UCF file to define pins and place RTL PHY in specific LUTs, etc., with
full set of constraints


PHY auto
-
calibrates:


Calibrates delay lines to keep delayed DQS correctly
aligned across temperature/voltage variations

BEFORE laying out board!

PHY: Memory Interface Generator (not using MCB)

What MIG Generates

(for all but S6, S6 MCB is a hard
-
core)

MCB Calibration Steps

MPMC

From Xilinx MPMC datasheet

PHY
from
MIG

MPMC:
M
ulti
-
P
ort
M
emory
C
ontroller


Memory controller provided by Xilinx


Memory
-
side:


Provides interface to SDRAM, DDR, DDR2, DDR3, LPDDR
memories


Fabric
-
side:


8 Interfaces made available to FPGA fabric:


PLB interface


Xilinx Cache Link (XCL)


PowerPC interface


Video Frame Buffer Controller (VFBC)


Native Port Interface


MPMC handles the prioritization between parallel accesses
to the external memory

Personality Interface Modules (PIMs)


Xilinx
CacheLink

PIM (XCL):

Provides a near direct connection to the
MicroBlaze

processor cache.


Soft Direct Memory Access Controller PIM

(SDMA): A 32
-
bit wide Xilinx Local Link
interface provides medium
-
throughput performance, but offloads CPU
involvement with hardware scatter
-
gather handling. Typically SDMA is used only
with an XPS_LL_TEMAC core.


Processor Local Bus PIM (PLB):

A general interface used on most EDK IP cores. The
PLB is suggested to be used for the most forward
-
compatibility.


PowerPC 440 Memory Controller PIM (PPC440MC):

Provides lowest latency
connection when using the Virtex
-
5 PowerPC 440 processor.


Video Frame Buffer Controller PIM (VFBC):

A two
-
dimensional DMA core. High
-
latency, but high
-
throughput operation for very long bursts, such as entire video
frames.


Native Port Interface PIM (NPI):

The highest performance general PIM. All other
PIMs except for MCB connect through an NPI interface.


MCB PIM (MCB):

Spartan
-
6 only PIM providing raw access to the hardened
memory controller for highest performance.

From Xilinx MPMC datasheet

MPMC Configuration

These ports are exposed to external FPGA
fabric.

Example MPMC Use Case

XCL

VFBC

VFBC

MPMC

VFBC

VFBC

XCL

DDR Memory

VGA

Camera

Convolution Core

Microblaze

MPMC PHY

AXI IP Interconnects

Xilinx MCB

Memory Controller Block (MCB)

Adding MCB with BSB

Adding Cache to the MB

MCB Configuration (1)

MCB Configuration (2)

MCB Configuration (3)

MCB Configuration (4)

MCB Configuration (5)

Xilinx MCB

OLD MPMC SLIDES

From Xilinx MPMC datasheet

MPMC Configuration

These ports are exposed to external FPGA
fabric.

MPMC Port Configuration

Physical Interface Layer


Physical Interface Layer “performs the calibration and
signaling to the external memory device”.


PHY options available:


Xilinx MIG:


Recommended interface for all FPGAs but Spartan 6


Generated interface placed in specific FPGA resources to meet timing


Pin settings must be chosen during PCB design


Spartan 6:


Hard
-
core memory interface


Static PHY:


“Last
-
choice” memory interface


Includes clock
-
adjustment control so user can self
-
calibrate the clock
-
phasing

PHY: Memory Interface Generator

MIG: Setting Pin Locations

Designing With MPMC


Design memory interface
before

laying out
board



Select FPGA and memory



Using MIG before laying out board, determine
required location for all memory interface
signals

RST_DQS_DIV

Source: xapp454, DDR2 SDRAM Interface for Spartan
-
3 Generation FPGAs

The

FIFO

write

enable

signal

is

generated

from

a

signal

named

rst_dqs_div
.

Figure
4

illustrates

the

idea

behind

rst_dqs_div
.

The

rst_dqs_div

signal

is

driven

to

an

IOB

as

an

output

and

is

then

taken

as

an

input

through

the

input

buffer
.

This

technique

normalizes

the

IOB

and

trace

delays

between

rst_dqs_div

and

the

DQS

clock

signals
.

The

rst_dqs_div

from

the

input

pad

of

the

FPGA

uses

identical

routing

resources

as

the

DQS

before

it

enters

the

LUT

delay

circuit
.

The

trace

delay

of

the

loop

should

be

the

sum

of

the

trace

delays

of

the

clock

forwarded

to

the

memory

and

the

DQS
.


Oops

UCF/Timing Report

##############################################################################################################

## Constraint from
rst_dqs_div_in

PAD to input of LUT delay element.

##############################################################################################################

NET "*/DDR_SDRAM_MT46V16M16_5B/mpmc_core_0/gen_??_ddr_phy.mpmc_phy_if_0/
dqs_div_rst
" MAXDELAY = 468
ps
;



================================================================================

Timing constraint: NET

"
Inst_processor
/DDR_SDRAM_MT46V16M16_5B/DDR_SDRAM_MT46V16M16_5B/mpmc_core_0/

gen_s3_ddr_phy.mpmc_phy_if_0/
dqs_div_rst
" MAXDELAY = 0.468 ns;



1 net analyzed, 1 failing net detected.


1 timing error detected.


Maximum net delay is 2.549ns.

--------------------------------------------------------------------------------

Slack:
-
2.081ns
Inst_processor
/DDR_SDRAM_MT46V16M16_5B/DDR_SDRAM_MT46V16M16_5B/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/
dq
s_div_rst

Error: 2.549ns delay exceeds 0.468ns timing constraint by 2.081ns

From To Delay(ns)

AB5.I SLICE_X0Y70.G3 2.499

AB5.I SLICE_X1Y70.F3 2.448

AB5.I SLICE_X1Y70.G4 2.481

AB5.I SLICE_X1Y71.G2 2.549

--------------------------------------------------------------------------------

Adding Memory (Roughly)


Add a MPMC


During this process, add a memory that matches your part as closely as
possible; update to match exactly


This adds a memory to the MB, as well as the memory controller PHY, but
without constraints


Create a new Memory PHY in the ISE project


During this process, add a memory that matches your part as closely as
possible; update to match exactly


Choose the banks where you would like the memory to go


Generate


Go back and edit to match your pins exactly; check with memory generator


Take the UCF from the Memory PHY, and map to the MPMC PHY


xilperl

C:
\
Xilinx
\
10.1
\
EDK
\
hw
\
XilinxProcessorIPLib
\
pcores
\
mpmc_v4_03_a
\
data
\
con
vert_ucf.pl
--
mhs


\
processor.mhs

\
mem_phy
\
user_design
\
par
\
mem_phy.ucf …
\
new.ucf


Incorporate into your UCF

BACKUP

DDR2 SDRAM Interface Module

Source: xapp454, DDR2 SDRAM Interface for Spartan
-
3 Generation FPGAs