Practical Applications For CLD - Central Semiconductor Corp.


Nov 1, 2013 (3 years and 9 months ago)


Semiconductor Monthly
49 • ECN  May 15, 2000
Edited by Aimee Kalnoskas,
Practical Applications of Current Limiting Diodes
by Sze Chin, Central Semiconductor Corp.
he current limiting diode (CLD) or current regulating diode (CRD) has been available since the
early 1960’s. Unfortunately, despite its simplicity and distinct advantages over conventional
Silicon V alley D i r e c t
transistorized applications, it has seen only limited use. One reason may be designers’ lack of
familiarity with practical circuit design techniques involved with its use. Another reason may be that
although many papers have been published on the device, most have dealt primarily with solid-state the- Spring Products
ory, rather than with practical applications. Therefore, it is the purpose of this paper to focus on how this
device is used, rather than on what it is. by Carol Rosen,
Western Regional Editor
emiconductor designers have been busy designing and
developing a host of new ICs to speed systems, lower power
Conventional Constant Current Source vs. CLD
S or make building a system easier and less costly. As the IC
From basic circuit theory, an ideal current source is one with infinite output impedance. The term
economic picture continues to improve, capacity for most lines (with
constant current source usually applies to a circuit that supplies a DC current whose amplitude is inde-
the exception of dynamic RAMs and some flash memories) is abun-
pendent of a change in either load or supply voltage. dant although demand continues quite heavy.
Analysts expect that the spring and summer months will contin-
ue to be active with many IC makers getting new devices to market
Basic Constant Current Circuit as quickly as possible in order to garner as much in sales as possible.
The simplest circuit is a voltage source in series with a resistor
-V )/R . The current would
as shown on Fig. 1. The current is (V
PLX Releases New Design Tools
change very little if the load voltage, V , is small compared with
, and the source resistance, R , is much PLX Technology, Inc. recently announced expanded design sup-
the supply voltage, V
. When the load voltage is in
larger than the load resistance, R port for PCI- and CompactPCI-based products. The PCI 9030RDK-
the order of several volts and accuracy within a few percent is LITE and CompactPCI 9030RDK-LITE reference design kits simpli-
has a mag-
required, the circuit in Fig.1 can be achieved only if V fy the development of PCI adapter designs incorporating PLX’s

nitude of several hundred volts. This may be feasible, but is PC9030 SMARTarget
Fig. 1. Basic Constant Current
Circuit impractical. accelerator.
The new tools each
Transistor Constant Current Source offer a basis for PCI and
For a constant current source, the use of a transistor as shown CompactPCI hardware
in Fig.2 would eliminate the need for a high voltage source. This and software development
circuit provides a constant current of approximately 10 mA, which using the PCI9030. The
is determined by the current through R , and in turn on the volt- kits also offer complete
age across R , i.e. V *R /[(R + R )R ]. Since I =I =I =I , The load development environ-
2 S 2 2 3 1 R1 E C L
current, I , is also V *R /[(R + R ) R ]. This current will maintain ments to allow designers
L S 2 2 3 1
its constant amplitude provided the transistor is not saturated, i.e. to migrate previous gener-
V V *R /(R +R ation designs to those with
L 3 2 3
As the load, R , changes, the collector voltage of Q will change, PCI9030, including
L 1
but the collector current will change very little because its dynamic CompactPCI boards.
impedance, r , is very large, typically at 1 MΩ . The transistor oper- The kits include refer-
ates like a current source with resistance, r . A non-transistor ence design boards and a
source would require a supply in the range of hundreds of volts to PLX host software devel-
equal this performance. opment kit (SDK). Each PLX Technology recently
Fig. 2. Transistor Constant
announced two reference design
Even though the Fig. 2 circuit represents a great improvement kit contains a PCI v2.2-
Current Circuit
kits for use with its PCI9030 chip.
over that of Fig. 1, there are still limitations on its performance, compliant PCI board
such as temperature drift associated with both resistor and tran- (PCI9030RDK-LITE) or
sistor parameters, notably the V and the leakage I . Also, any CompactPCI board (CompactPCI9030RDK-LITE) based on the
variation of V will cause a change in the bias voltage; therefore, PCI9030 chip. The kits also offer comprehensive
will affect the constant current. QFP/BGA/SSOP/TSOP/PLCC/SOIC footprints and prototyping area
for developing, debugging and testing. Other features include up to 8
Stabilized Current Source
K 32 dual-port SRAM, RS-232 serial port, six logic analyzer test
Fig. 3 shows a stabilized version of the Fig. 2 circuit. In this
headers, PLX option module connector, ISA connector footprint for
of Fig. 2. The zener is equivalent
circuit, a zener diode replaces R designing PCI9030 into an ISA application and a CompactPCI form
z, which is typically
to a battery in series with a low resistance, R factor that is both 6U and 3U capable.
20Ω . This current has great stability against variation in the sup- The tools also provide a hardware development kit CD-ROM con-
)] of
ply voltage, V . In the Fig. 2 circuit, 50 percent [ R /(R + R taining all necessary hardware design information and documenta-
S 2 2
the change in V would affect the Q bias, whereas in the Fig. 3 tion. They include a host SDK CD-ROM with Windows 98/2000/NT
S 1

/(R + R )] of a V change is felt on 2000 debugger with an EEPROM configu-
circuit, only 0.04 percent [R device drivers, PLXMon
Z Z 3
the Q bias . ration screen and customizable hot links and comprehensive host
Fig. 3. Stabilized Current
A low temperature coefficient zener may be used in this cir- API library and a sample PCI9030 chip.
Source Circuit
cuit. Many zeners with temperature coefficients of + 0.1%/°C or Available this quarter, the PCI9030RDK-LITE is priced at $299
less are available. To further improve stability against tempera- and the CompactPCI9030RDK-LITE is priced at $495, both with the
ture drift, a PCI host SDK. PLX Technology, 390 Potrero Ave., Sunnyvale,
diode may CA 94086; (800) 759-3735;
be added in
Write in 1373 or
series with
Xilinx Offers PLDs in New Technology
the zener,
thus com- Xilinx, Inc. recently announced new FPGAs fabricated in a new
pensating copper process technology. Xilinx and UMC Group have collaborated
for the V on copper interconnect technology for the last two years. That tech-

drift. nology is the foundation for Xilinx’s new Virtex -E extended memo-
Fig. 4a. FET Constant Current Fig. 4b. CLD Volt-Ampere ry (Virtex-EM) FPGA.
Source Characteristics
Copper interconnect offers lower resistivity, minimizing power
supply drop throughout the FPGA. The new family uses a 0.18
micron, six-layer metal process with the top two layers deploying
copper interconnect. Those top layers are used to route clock lines to
decrease clock and I/O skew for optimized performance.
continued on page 50 continued on page 5350  ECN  May 15, 2000
Semiconductor Monthly
Discrete Semiconductors
continued from page 49
For Q , since the emitter current is the same:
o / e = + 1/2 R / [r + (r + R ) /β
2 in1 L e b1 S1 1)
The voltage gain of Q is the same as Q , but opposite in sign.
2 1
If the bias resistor, R , is finite, it has a parallel effect on the impedance (r + r /β
E e b
/β) of Q . Hence is changed from 1/2 e to 1/2 e [R / (R + r + r /β +
+ R
S 2 E in1 in1 E E e b
/β] and thus is slightly smaller. Q ’s emitter current therefore is increased, and
S E 1
’s emitter current is decreased. This implies that Q ’s gain is higher.
2 1
e , its effect is equal but opposite to that of
With regard to the source signal
e . Hence
/ e = - 1/2 R / [r + (r +R ) /β]
2 in1 L e b S
Figure 5a. Simplified Cross Figure 5b. CLD Symbol
/ e = + 1/2 R / [r + (r +R ) /β]
1 in2 L e b S
Section View of N-Channel FET
With both e and e present, the output voltage can be shown by superposition to
in1 in2
Current Limiting Diode (CLD) = - 1/2 e ( R ) + 1/2 e ( R )
1 in1 L in2 L
r + [(r + R ) /β]
r + [(r + R ) /β]
The CLD or constant current diode is basically a junction FET transistor operating
e b S e b S
It follows that:
with its gate shorted to the source terminal, as shown in Fig. 4a.
In this configuration, the JFET exhibits a unique current-limiting characteristic as

V is increased until the FET’S voltage breakdown limit is reached. This current-limit- = 1/2 (e - e ) R , and = 1/2 (e - e ) R
DS 1 in2 in1 L 2 in1 in2 L
o o
r + [(r + R ) /β]
ing characteristic is shown in Fig.4b. In order to explain the Fig. 4b characteristics, a
r + [(r + R ) /β]
e b S
e b S
cross section of the N-channel JFET is shown in Fig. 5a.
is applied, a voltage drop, V , The above shows that if e = e , then = = 0; and if e = -e , then the
When the drain current begins to flow as voltage V
DS RDS in1 in2 1 2 in1 in2
o o
is developed along the channel. This voltage drop provides a reverse bias on the PN above becomes
= - e ( R ) , = + e ( R )
junction between the gate and channel. Space charge or depletion regions are generated
1 in1 L 2 in2 L
o o
r + [(r + R ) /β]
is increased, the increase in current causes more
and spread into the channel. As V e b S
r + [(r + R ) /β]
e b S
The amplifier thus produces equal and opposite outputs based upon the difference
reverse bias. Hence, the depletion regions grow until they meet, at which point any fur-
will be counter-balanced by an increase in the depletion region
ther increase in V between the two input signals, but independent of their sum.
e = e , and R is finite, then the current in Q and Q is no longer constant,
toward the drain. When this condition is reached, the current has reached its limiting If
in1 in2 E 1 2
condition. The V voltage that causes the current to reach limiting condition is called and a total change of e /R results. Each transistor’s current changes by 1/2 e /R ,
DS in1 E in1 E
V , the pinch-off voltage. with a resulting output change of - 1/2 e R /R , out of phase with e . A finite R
P in1 L E in1 E
When a JFET is used as a CLD, its symbol becomes that shown in Fig. 5b. The drain would result in appreciable output, even when e = e .
in1 in2
becomes the anode, “A”, and the source becomes the cathode, “K”. When a differential amplifier is used to measure the difference of two signals, the cri-
Because of its unique current-limiting characteristics, i.e. very large dynamic imped- teria for performance is the ratio of the gain due to the difference to the gain due to the
ance (typically in the megohm range), and low temperature drift (as compared with the sum of the two input signals, known as common mode rejection, or CMR.
transistor), the CLD’s advantages over transistors in current-limiting application are V V .
out out
obvious. Moreover, a single CLD replaces five components in the transistorized version (e - e ) (e + e )
in1 in2 in1 in2
to achieve the same performance as a constant current source.
~ 2 R ~ 2 R
r + [(r + R ) /β]
Market Availability Of CLD’s 1/g + R /β]
e b S m S
Today, CLD’s are available with current ranges from 35 A to 15 mA and associated
~ ~
impedance values from over 20 MΩ to several hundred KΩ . Their peak voltage rating For the Fig. 6 circuit, 1/g ~ 50Ω , β ~ 50
ranges from 50 to over 100V. Temperature coefficients are typically within 0.3%/°C.
Near the 1 mA level, the T is close to 0% per °C. The low-cost CCL0035-CCL5750 series Hence, CMR = 2 (10K) = 385.
from Central Semiconductor has a current range from 35 A to 6 mA, with peak voltage 50+100
ratings of 100 V, and peak power at 600 mW in a DO-35 package. The CCLH080 - 50
CCLH150 series, also in a DO-35 package, provides 6 mA to 15 mA, with a peak voltage
rating of 50 V, and peak power of 600 mW. The use of CLD’s is limited only by one’s If a 1 mA CLD is used for R , as shown in Fig. 8 (page 52), and since the Z for such
E d
imagination in the application of the basic laws of electronics. a CLD is typically 1 Meg Ω ,
Then: One can see the signifi-
CMR = 2(1,000,000) = 38,461 cant improvement in
Differential 52 CMR by a factor of more
Amplifiers than 100X with the CLD.
Today’s most popular
amplifier is the differential
amplifier because, theoreti-
cally, it responds only to the
difference of two signals, and
is inherently temperature
stable. The common-mode
rejection ratio, CMR, is nor-
mally a measure of its perfor-
mance — i.e. the higher the
Fig. 7. Equivalent AC
CMR, the better a device’s
Circuit with e = 0 &
performance. Presented in
e = 0
Fig. 6 is a standard differen-
Current Amplification & Division
tial amplifier circuit and in
Even though the current range of the CLD is limited to less than 15mA, this current
Fig. 7 is an AC equivalent
Fig. 6. Differential Amplifier
circuit, which will be used to may be practically amplified to a higher level. Shown in Fig. 9 is a circuit using an op-
show how the CMR may be greatly improved by incorporating a CLD to provide a con- amp to either amplify or attenuate a CLD’s current level.
stant bias current. Since an ideal op-amp has infinite input impedance, its input currents IN+
To simplify the analysis, transistors Q and Q are assumed identical, R = R and IN - are zero, and its differential input V = 0. Therefore,
1 2 S1 S2 IN
R =R , and RE >>(R /β + r /β + r ). With e present and e shorted to ground, the
L1 L2 S b e in1 in2
signal, , at terminal E would be 1/2 of e , since the impedances looking toward the = V
in1 R1 R2
emitters of Q & Q are the same. Hence I R = I R
1 2 R1 1 R2 2
= 1/2 e . Therefore Since IN- = 0, I = I
E in1 R1 CLD
i = (e .- ) = 1/2 e . / [(r + (R + R ) /β ] And since IN+ = 0, I = I
E1 in1 E in1 e b1 s1 1) R2 RL
Hence I R = I *R
CLD 1 RL 2
Since o = - i R , the voltage gain I = I R
1 E1 L1 RL CLD 1
o / e = - 1/2 R / [r + (r + R ) /β ] R
1 in1 L e b1 S1 1) 252  ECN  May 15, 2000
Semiconductor Monthly Discrete Semiconductors
continued from page 50
as shown on Fig. 11b, it becomes a pulse with a known reference amplitude, which can
be used in a pulse-generator design.
Ultra High-Speed Pulse Amplitude
Shown in Fig. 12 is a high-speed pulse amplitude reference circuit. The amplitude of
1 volt is generated by a 10mA CLD through 100 ohms. The rise and fall times are less
than 10 nS, achieved with the use of Schottky diodes as switches, driven by an ultra-
high-speed op-amp.
, is driven by a digital TTL pulse signal. When the sig-
In this circuit, the Op Amp, U
’s output goes high, and diode D is reverse biased and turned off,
nal goes to logic “0”, U
1 3
, onto R . As the TTL signal goes
thus allowing the constant current through diode, D
2 1
’s output goes low, thus forward-biasing D and reverse-biasing D . Hence, the
high, U
1 3 2
Fig. 8. CLD Replacing R current to R is switched off. The result is a reference pulse with precision amplitude.
E 1
Fig. 9. Current Multiplying/Dividing Circuit
This shows that the CLD’s current level may be amplified or attenuated by the
ratio of resistors R and R . The maximum load current is limited by the Op
1 2
Amp’s current capacity - i.e. for a given I , the maximum R is limited by the
input voltage rating of the Op Amp, such that I R max. input voltage rating.
There are many Op Amp’s available with current ratings up to several hundred mA,
and with input voltage ratings up to 15 V. Their input voltage offsets range from a few
Fig. 11a. Voltage Reference Fig. 11b. A Pulse Amplitude Reference
V down to a few V, and input offset currents from 1 A down to less than 1 nA. Hence
the use of a high performance Op Amp provides very accurate current amplification or
= 1 mA, R = 1K and R =100. If R /R =10, Other Applications
attenuation. Assume, for example, that I
CLD 1 2 1 2
is amplified 10 times, allowing 10 mA to the load. If the input offset were 1 These are three versions of Ohm’s law, namely:
then I
V, this would cause only a 0.1% error. And if the input offset current were 10 A, this
= iR, i = C dv and v = L di
would still cause only a 0.1% error.
dt dt
Resistance Measurement So far, only the = iR version has been used in this presentation of practical applica-
The Current Amplifying/Dividing Technique shown above may be easily applied to
resistance measurement. The measurement circuit, if digitally controlled and pro-
grammed, may become part of an automatic test equipment (ATE) system.
From the basic formula V = IR , the voltage, V , is proportional to the unknown
resistance, R . If I is known, the unknown R may be found by reading the voltage V .
Referring to the Fig. 9 circuit, if we select R such that I x R =1V, the voltage on R
1 CLD 1 2
is also 1V.
Hence I
R = 1V
R2 2
I R = V
R2 x
R = R V
X 2 X
If R is selected in multiples of 10, and V is limited to 1V maximum, then the
2 x
unknown, R , may be read directly on a decimal scale. Fig. 12. Ultra High speed Pulse Amplitude Reference.
Editor’s Note: opamp preceeds U1
=CL200 or Equivalent.
For example if R is:
tions. As for the other two versions, =L di/dt is not relevant, since di/dt for a constant
100 Ω , Rx = 100 Vx
current device is zero. The remaining applicable equation is: i =C dv/dt. Presented next
1,000 Ω , Rx = 1,000 Vx are some suggested uses of this formula.
10,000 Ω , Rx = 10,000 Vx From i = c dv/dt, if i is constant, then is a ramp function. This means that if a con-
100,000 Ω , Rx = 100,000 Vx stant current is switched into a capacitor, as shown in Fig. 13a, a ramp voltage which
1,000,000 Ω , Rx = 1,000,000 Vx increases linearly with time is generated, as shown in Figure 13b.
If the switch is added across the capacitor as shown in Fig. 14a, and the switch is
The above shows that if the five resistor values from 100 Ω to 1MΩ are incorporated closed for some period, then opened for some other period, the output, V , shown in Fig.
for R2, effectively the circuit of Fig. 9 is now transformed into a resistance-measuring 14b is a sawtooth waveform whose shape depends on the closed and open periods of the
circuit with 5 decimal scales capable of measuring resistances up to 1 MΩ in five ranges.
Fig. 10 shows such a transformed circuit with discrete components and values.
This circuit may be auto-
mated with an A-D converter
to convert Vx into Digital
Data. Selection of the proper
scale may be achieved through
auto-ranging techniques under
digital control.
Fig. 13a. Ramp Circuit Fig. 13b. Ramp Function
Voltage Amplitude
When a known constant
Assume that the switch is closed for a very short period, then opened for a fixed peri-
current flows through a od, and that this process is repeated indefinitely. The result would be a continuous saw-
known resistor, a known volt- tooth with constant peak amplitude as shown in Fig. 14c.
age is generated. This may be
used as a reference (as shown Application of Ramp Waveforms
in Fig. 11a) in many feedback It is not enough simply to know how to generate such waveforms; we must know how
control applications such as to apply them. Since the equation, = it, relates voltage to time, one can either use its
DC regulation, motor speed voltage characteristics to control time, or its time characteristics to control voltage.
control, automatic frequency-
control, and automatic gain- Automatic On/Off Time (T on/T off) Detection
control. When the voltage ref- The ramp function of Fig. 13b may be used for automatic Ton/Toff detection. Since
Fig. 10. Resistance Measuring Circuit erence is switched on and off, Ton/Toff is an important semiconductor parameter, the ability to test it automatically54  ECN  May 15, 2000
Semiconductor Monthly
Discrete Semiconductors
continued from page 52
would save the manufacturer time and
money. As shown in Fig. 13b, the V
amplitude is proportional to time. At
, the V level is at V . If T repre-
time T
1 C 1 1
sents a transistor’s maximum T
on off
time, then we can use V as a reference
for comparison with the peak voltage of
/T time of
a ramp corresponding to T
on off
the transistor under test. If the V
, the detection circuit’s output would
Fig. 14a. Sawtooth Circuit
indicate failure, or vice versa. Fig. 15
shows a simplified version of
such a detection circuit.
Fig. 17. Simplified Switching Regulator Circuit
Pulse Width
When a sawtooth or triangu- ±10 V, and acquisition time of 1.5 µS max, a staircase waveform is generated that can be
lar signal is compared with a DC used for voltage level control or discrimination.
signal, a pulse signal may be
Fig. 14b. V = 0 when SW closed, V > 0 generated. The pulse width, PW,
when SW open Conclusion
may be varied or modulated if the
The Current Limiting Diode, offer-
level of the DC signal is varied.
ing simplicity and high performance
characteristics when compared with a
bipolar transistor, has been shown to
offer versatility in many circuit appli-
cations, as well as superior perfor-
mance regarding temperature drift
and dynamic impedance.
Fig. 14c. Sawtooth waveform with constant period, T, and constant V .
1. Field-Effect Transistors
Wallmark and Johnson,
Prentice- Hall, 1966
2. Field-Effect Transistors
Leonce J. Sevin, Jr. McGraw
Hill, 1965 Fig. 18a. Staircase Generator Circuit
3. Operational Amplifiers
Tobey, Graem, Huelsman,
McGraw Hill, 1971
4. Electronic Designer’s
T.K. Hemingway, Tab Books,
5. Motorola Semiconductor Data
Fig. 15. Automatic T /T Detection Book, 1969
on off
6. Burr-Brown Product Data
Book, 1984
Shown in Fig. 16a is a simple pulse width modulator (PWM), with output waveforms 7. Central Semiconductor Data
for two DC signal levels shown in Fig. 16b. Book, 1998
This pulse width modulator may be used as part of any feedback loop to control the
proper function of an electronic apparatus such as a servo amplifier, switching regulator,
phase controller, or a voltage-controlled oscillator.
Using a switching regulator as an example, its DC output is proportional to the
duty cycle of the switching device that chops its DC input signal. When its DC output
is compared with a reference sawtooth through a pulse width modulator, the pulse
width of the PWM will vary in such a way that the DC output is maintained within
Fig. 18b. Sample & Hold Output Waveform
its accuracy range. Shown in Fig. 17 is a simplified sketch of a PWM used within a
switching regulator.
Sze Chin is Senior Applications Engineer
for Central Semiconductor Corp. Mr. Chin
holds a B.S.E.E. from Rensselaer
Polytechnique Institute. He has been
designing Analog and Digital circuits for
over 30 years for such companies as
Grumman, NCR, IBM and General
Dynamics. For more information contact
Sze Chin at Central Semiconductor Corp. 145 Adams Ave,
Hauppauge, NY 11788 USA Tel: (631) 435-1110; Fax: (631)
435-1824 or via email at:
Fig. 16a. Simplified Pulse Width Modulator Fig. 16b. PWM Output Waveforms
Write in 1466 or
Staircase Generator
A staircase waveform may be generated through the use of a sample and hold tech-
nique as shown in Fig. 18a. If various levels along the ramp are sampled and held, a Write in Number or Reply Online
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staircase waveform is generated as shown in Fig. 18b. The length of each step depends
on the droop rate of the sample and hold amplifier. Using a Burr Brown SHC5320 Very Useful Useful Not Useful
1467 1468 1469
device as an example, with a droop rate of ±0.5mv/mSec max, output voltage range of