[Ph.D.-afhandling] Energy Transport Models for

Numerical Simulations of Semiconductor Structures

In the recent years, we have noticed a dramatic increase of the operating frequency and decrease of size of electronic

devices due to a strong market demand for higher speed, lower power consumption, and better functionality of

microelectronic systems. Higher operating frequency requires miniaturization, i.e., shrinking of the characteristic sizes of

electronic components as well as the connections between them. Lower power consumption means lower heating which

allows higher integration density and longer autonomy of the systems. Better functionality usually means higher system

complexity per unit area which again forces decrease of the characteristic sizes.

Nowadays, modern semiconductor electronic devices and base elements for functional building blocks of ultra-large scale

integrated electronic circuits have the characteristic lengths into nanometer scale regime (1 – 100 nm). In that regime,

the quantum-mechanical phenomena occur together with new material properties while fabrication of the nanodevices is

influenced by statistics. Hence, the electrical “behavior” of the nanodevices cannot be described by classical physical laws

and fluctuations of electrical properties of advanced microelectronic systems are expected. Apart from that, fabrication

technology is usually not able to follow the edge of theoretical investigations.

Nanotechnology literally means any technology performed on the nanometer scale that has applications in the real world.

Nanotechnology is a wide area and includes production and application of physical, electrical, chemical, biological, and/or

hybrid systems ranging in size from a fraction of nanometer to 100 nm. A number of different technologies and chemistry

techniques are used to produce semiconductor nanodevices. They are mainly based on so-called bottom-up approach

which is opposite from conventional top-down approach.

In general, electrical properties (e.g., the current-voltage characteristics) of the semiconductor devices can be either

measured or simulated. The more and more complicated and time-consuming fabrication processes and problems related

to the actual operation of the low-dimensional devices make a pure experimental “trail-and-error” optimization approach

almost impossible since it is too time-consuming and too expensive. At the same time, with strong progress of advanced

microelectronics, computers become more and more powerful, faster, and cheaper resources. Therefore, mathematical

modeling based on the physical laws and numerical simulations of semiconductor devices become more and more popular

scientific tools.

Computational electronics refers to the mathematical modeling, which is strongly based on the physics occurring in the

low-dimensional semiconductor structures, followed by the numerical analysis and simulations. Hence, computational

electronics nowadays becomes an indispensable and plausible scientific tool for investigations and optimizations of

semiconductor nanodevices. Besides offering the possibility to test hypothetical semiconductor nanodevices which

can/cannot be fabricated, computational electronics offers unique insight view into the device behavior by allowing the

investigations of the phenomena that certainly cannot be measured or observed (from outside) on the real devices.

The main idea regarding the modeling is to make device simulations as simple as possible making them as fast as possible.

At the same time, to make the simulations reliable, they should be accurate enough to allow study of the electrical

properties of real semiconductor devices at least in the qualitative sense. However, accuracy comes together with

complexity while complexity increases requests for the computational resources and time. Hence, optimization regarding

accuracy and complexity is necessary. Device simulators, in general, solve a system of equations with specified

geometrical and physical parameters of the device and defined initial and boundary conditions. Those equations usually

form a highly nonlinear system of coupled partial differential equations which cannot be solved analytically. Hence,

different numerical methods have to be used in order to calculate a solution by discretizing the system of equations on

suitable temporal mesh and spatial grid.

Semiconductor devices which rely on quantum-mechanical tunneling through potential barriers and accumulation of the

electrons in the quantum wells are playing increasingly important role in advanced microelectronic applications. Those

resonant tunneling semiconductor heterostructures, including heterostructure nanowires, have an active region which

consists of a few nanometers thin layers made of different semiconductor materials. They have potential to become the

most important semiconductor devices and elements of sophisticated state-of-the-art electronic circuits due to their fast

intrinsic operation and high-speed switching. Hence, they attract a lot of attention from both fundamental and engineering

points of view.

Our idea is to use a relative simple macroscopic model which accounts for the lowest order quantum-mechanical effects

and to investigate semiconductor heterostructures in dimensions higher than one. First, we have studied hierarchy of the

macroscopic models with and without quantum-mechanical corrections. Then we chose a macroscopic model with quantum

correction and investigated its limitations, drawbacks, validity, and physical correctness of the results in one dimension

performing comparisons with a full quantum-mechanical model and experimental data. Numerical investigations of the

heterostructure nanowire in two dimensions show usefulness of chosen model and obtained results give a good starting

point for further research activities. Apart from that, used full quantum-mechanical model has been investigated and

suggestions for its improvement have been demonstrated. Natural idea of hybrid modeling employing those two models

has been raised and discussed.

Kontaktperson Lone Kjærgård Larsen, e-mail loj@adm.sdu.dk

(2006-02-07)

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