is a family of microcontroller
separate program memory
and data memory.
Made by Microchip Technology.
end PIC Architectures :
Microchip PIC microcontrollers
PIC microcontroller was first available from General
Instruments in early 1980's
consisted of a simple
processor executing 12
bit wide instructions with basic I/O
functions, known as low
They have limited program memory and are meant for
applications requiring simple interface functions and small
program & data memories. Some of the low
numbers are 12C5XX
, 16C5X, 16C505
Mid range PIC Architectures
Built by upgrading low
end architectures with more
number of peripherals, more number of registers and
more data/program memory. Some of the mid
Program memory type is indicated by an alphabet.
C = EPROM
F = Flash
RC = Mask ROM
The PIC architecture is characterized by
Separate code and data spaces (Harvard architecture)
for devices other than PIC32, which has a
A small number of fixed length instructions
Most instructions are single cycle execution (2 clock
cycles, or 4 clock cycles in 8
bit models), with one
delay cycle on branches .
accumulator, the use of which (as source
operand) is implied (i.e. is not encoded in the
All RAM locations function as registers as both source
and/or destination of math and other functions.
A hardware stack for storing return addresses
A fairly small amount of addressable data space
(typically 256 bytes), extended through banking
Data space mapped CPU, port, and peripheral registers
The program counter .
There is no distinction between memory space and
register space because the RAM serves the job of both
memory and registers.
RAM is usually referred to as the register file or simply
as the registers
Data Space (RAM)
PICs have a set of registers that function as general purpose
Special purpose control registers for on
resources are also mapped into the data space.
All PIC devices have some
banking mechanism to extend
addressing to additional memory.
To implement indirect addressing, a "file select register"
(FSR) and "indirect register" (INDF) are used.
External data memory is not directly addressable except in
some high pin count PIC18 devices.
The code space is generally implemented as
External code memory is not directly addressable due
to the lack of an external memory interface.
All PICs handle data and address in 8
The unit of addressability of the code space is not generally
the same as the data space.
For example, PICs in the baseline (PIC12) and mid
(PIC16) families have program memory addressable in the
same word size as the instruction width.
In the PIC18 series, the program memory is addressed in 8
bit increments (bytes), which differs from the instruction
width of 16 bits.
The program memory capacity is usually stated in number
of (single word) instructions, rather than in bytes.
PICs have a hardware
called stack which is used to save
The hardware stack is not software accessible on
earlier devices, but this changed with the 18 series
CPU Architecture of PIC
A PIC's instructions vary from about 35 instructions for the low
PICs to over 80 instructions for the high
The instruction set includes instructions to perform a variety of
operations on registers directly, the
and a constant or the
accumulator and a
PIC cores have skip instructions which are used for conditional
execution and branching. The skip instructions are 'skip if bit set' and
'skip if bit not set'. Because cores before PIC18 had only unconditional
A few miscellaneous zero
operand instructions, such as return from
to enter low
In general, PIC instructions fall into 5 classes:
Operation on working register (WREG) with 8
immediate ("literal") operand.
Operation with WREG and indexed register. The result can
be written to either the Working register or the selected
Bit operations. These take a register number and a bit
number, and perform one of 4 actions: set or clear a bit,
and test and skip on set/clear. The latter are used to
perform conditional branches. The usual ALU status flags
are available in a numbered register so operations such as
"branch on carry clear" are possible.
The PIC architectures have these advantages:
Small instruction set
Built in oscillator with selectable speeds
Easy entry level, in circuit programming plus in circuit
Wide range of interfaces
PSP, and Ethernet
is required to access the
entire RAM of many devices
Operations and registers are not
instructions can address RAM and/or
constants, while others can only use the accumulator
The hardware call stack is not addressable, so
cannot be implemented
are not efficient so
With paged program memory, there are two page
Popularity of the PIC microcontrollers is due to the following factors.
Speed: Harvard Architecture, RISC architecture, 1 instruction cycle = 4 clock cycles.
Instruction set simplicity: The instruction set consists of just 35 instructions (as opposed
to 111 instructions for 8051).
reset and brown
out reset. Brown
reset means when the power supply
goes below a specified voltage (say 4V), it causes PIC to reset; hence malfunction is
A watch dog timer (user programmable) resets the processor if the software/program
ever malfunctions and deviates
from its normal operation.
PIC microcontroller has four optional clock sources.
Low power crystal
Mid range crystal
High range crystal
RC oscillator (low cost).
Programmable timers and on
Up to 12 independent interrupt sources.
Powerful output pin control (25
(max.) current sourcing capability per pin.)
EPROM/OTP/ROM/Flash memory option.
I/O port expansion capability.
PIC 16F877 Architecture
Most common microcontroller
Does not have USB or built in network interfaces
Main program memory is flash ROM
stores a list of
14 bits instruction.
These are fed to execution unit and used to modify
RAM file registers.
Includes special control registers , port registers and
general purpose registers.
A separate working register (W) is used with ALU to
512 RAM file registers(000H
1FFH), organized in 4 banks.
Each bank contains 128 addresses.
bank 0 (0
7F), bank 1 (80
These contain SFRs and GPRs
Deducting SFRs from the total number of RAM locations ,
we get 368 bytes of GPRs
A to E
8 pins, C
8pins and E
giving total of 32 I/O pins
Most of them have more than
PIC 16F877 Architecture