Special applications of VLSI design - Universität Rostock

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Nov 2, 2013 (3 years and 11 months ago)

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Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
1

Spezielle

Anwendungen

des VLSI


Entwurfs


Applied VLSI design

Course and contest


Results of Phase 5


Nam Pham Van

Speed
Optimization

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Some

adder

structure

Slide 2

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Design
comparison (Synopsys)

Slide 3

2840
2860
2880
2900
2920
2940
2960
2980
3000
3020
RCA
Carry Skip
Carry Select
Brent Kung
Han Carlson
f [MHz]

adder

frequency
Condition:


Supply voltage 1.2 V


All libraries were used (CORE65LPLVT, CORE65LPSVT, CORE65LPHVT)







Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Chosen design

Slide 4

Han Carlson Adder (a parallel prefix adder):


Combination of Brent Kung &
Kogge

Stone structure


One of the faster adder


Suitable for VLSI


A = 0.5 * n * log(n)

T = log
2
(n) + 1





Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

How to achieve better speed performance?

Slide
5

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

At behavioral / design level

Improvement can be done with:


Pipelining


higher throughput





Array structures


Tree structures


Replication (parallelization)


Combinations of those



Slide
6

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Delay investigation
-

example inverter

Slide
7

0
0.2
0.4
0.6
0.8
1
1.2
0
100
200
300
400
500
600
700
T [ns]

W
[
nm
]

C = 1 fF
C = 10 fF
C = 25 fF
Low delay T with:


Lower capacitance C


Higher width W of the transistors (p
-
transistors 3x bigger than n
-
transistors)





Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Strategy:


Layout optimization




C
l




At the transistor level



ß


(
W

and
L

)


Supply voltage




V
dd



0

Technology optimization


Propagation Delay T :







t
r

: rise time










t
f

: fall time

T = (
t
r

+
t
f

) / 2







C
l

: capacitance










ß

: unity gain









V
dd

: supply voltage









W

: width









L

: length

Slide
8

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Voltage

& Libraries
comparison (Synopsys)

Slide 9

Condition:
All libraries

(CORE65LPLVT, CORE65LPSVT, CORE65LPHVT)


0
500
1000
1500
2000
2500
3000
3500
4000
CORE65LPLVT
CORE65LPSVT
CORE65PLHVT
f [MHz]

Library

Library
-

Frequency

frequency
Condition:

Supply Voltage 1.3 V

0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
1000
2000
3000
4000
f [MHz]

Voltage [V]

Voltage
-

Frequency

Voltage - Frequency
Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Chip
with

pads


Power (
P
dyn

/
P
leak
)

359.6078 mW / 6.2586 mW

Metric (J
-
2
)

[4.07989*
10
21
]

ASIC design


Cadence Encounter

Slide 10

Values
of

ASIC

Timing (
T
min

/
f
max
)

0.33
ns

/ 3030 MHz

Power (
P
dyn

/
P
leak
)

24.2087

mW / 9.1597 µW

# Pipeline Stages

8

Metric (J
-
2
)

[4.140*10
25
]

Core
size

5248 µm
2

Core
utilization

90

%

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Source

1.
Behrooz

Parhami
; „Computer Arithmetic


Algorithms and Hardware
Designs“, University of California

2.
Reto

Zimmermann; „Binary Adder Architectures for Cell
-
Based VLSI
and their Synthesis“

3.
Prof. Dirk
Timmermann
; „
Systemgerechte

Algorithmen
“,

Hochintegrierte

Systeme

I & II“,
Universität

Rostock

Slide
11

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Thank you for your attention!

Slide 12