RISC Processor Architecture

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Nov 2, 2013 (3 years and 9 months ago)

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RISC

CSS 548

Joshua Lo

RISC

Reduced Instruction Set Computers


Microprocessor architecture


Designed to perform a set of smaller
computer instructions so that it can operate
at higher speeds

What will we cover?


History


Theory


A
dvantages


Pipelining

Before the RISC era


Compilers were hard to build especially for machines with
registers


Make machine do more work than software


Have instructions load and store directly to memory (memory
-
to
-
memory operations)


Software costs were rising and hardware costs were
dropping


Move as much functionality to hardware


Magnetic core memory was used as main memory which
was slow and expensive


Minimize assembly code


Complex Instruction Set Computers (CISC)


Use complex instructions “MULT”, “ADD”…

Technology was advancing


Compilers were improving


Simple compilers found it difficult to use more complex
instructions


Optimizing compilers rarely needed more powerful
instructions


C
aches


allowed
main memory to be accessed at similar speeds to
control
memory


Semiconductor memory was replacing magnetic core
memory


Reduced performance gap between control and main
memory

Inception of RISC


1974


John
Cocke

(IBM) proved that 80% of
work was done using only 20% of the
instructions


Three RISC projects


IBM 801 machine (1974)


Berkeley’s RISC
-
I and RISC
-
II processors (1980)


Stanford’s MIPS processor (1981)


1986


announcement of first commercial
RISC chip

RISC Approach


Use only simple instructions that can be
executed within one clock cycle


Fewer transistors for instructions = more registers


Pipelining


Register
-
to
-
register operations


Operand reuse


Reduction of load/store

Pipelining

IF


Instruction Fetch

ID


Instruction Decode

OF


Operand Fetch

OE


Operand Execution

OS


Operation Store

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

Sequential

Pipelined

Clock Cycle

Clock Cycle

Time

Pipelining

IF


Instruction Fetch

ID


Instruction Decode

OF


Operand Fetch

OE


Operand Execution

OS


Operation Store

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

Data Dependency

IF

ID

O
F

O
E

O
S

IF

ID

O
F

O
E

O
S

Branch Address Dependency

IF

ID

O
F

O
E

O
S

Pipelining


Data dependencies can be addressed by
reordering the instructions when possible
(compiler)


Performance degradation from branches can
be reduced by branch prediction or executing
instructions for both branches until the
correct branch is identified

Other Advantages


New microprocessors can be developed and
tested more quickly if being less complicated
is one of it’s aims


Smaller instruction sets are easier for compiler
programmers to use

Use of RISC today


X86 is one of the only chips that retain CISC
architecture


Large base of proprietary PC applications were written
for X86 or compiled into X86 machine code


Intel was able to spend vast amounts of money on
processor development to offset the RISC advantages
enough to maintain PC market share


CISC and RISC architectures are nearly
indistinguishable


CISC processors use pipelining and can complete
multiple instructions per cycle


Transistor technology has allowed more room on
chips allowing RISC to have more CISC like instruction

Questions?

Al
-
Aubidy
, K (2010). Advanced Computer Architecture. Retrieved November 2012 from
http://www.philadelphia.edu.jo/academics/kaubaidy/uploads/ACA
-
Lect2.
pdf


Chen, C.,
Novick
, G., Shimano, K. (2000). RISC ARCHITECTURE. Retrieved November
2012, from http://www
-
cs
-
faculty.stanford.edu/~eroberts/courses/soco/projects/risc/about/
index.html


Joy, W. (1997). Reduced Instruction Set Computers (RISC): Academic/Industrial
Interplay Drives Computer Performance Forward. Retrieved
November
2012, from
http://homes.cs.washington.edu/~lazowska/cra/
risc.html


Merat
, F. (1996). PowerPC. Retrieved November 2012, from
http://engr.case.edu/merat_francis/eeap282f97/lectures/28_RISC%20&%
20PowerPC.
pdf


Patterson, D. A. (January 02, 1985). Reduced instruction set
computers.
Communications

of the
Acm
,

28,

1, 8
-
21
.


Rouse, M (2005). RISC (reduced instruction set computer).
Techtarget
. Retrieved
November 2012 from http://search400.techtarget.com/definition/
RISC