Presentation

basketontarioElectronics - Devices

Nov 2, 2013 (3 years and 9 months ago)

56 views

Outline


Overview


Specific Objective


Design Procedures


Summary

of GP1 Achievements


Background Theory


Detailed Design


Project Realization



Conclusion

Overview



Recently,

building

low
-
power

VLSI

systems

is

highly

in

demand




Most

of

the

VLSI

applications

such

as

digital

signal

processing,

image

and

video

processing

and

microprocessors

use

arithmetic

operations



CMOS

is

one

of

the

VLSI

electronics

that

used

in

microprocessors,

microcontrollers,

and

other

digital

logic

circuits

as

the

full

adder







Specific Objective


Full Adder


A full adder is a combinational circuit that forms the
arithmetic sum of three input bits


Input

Output

Cin

A
?
B
?
Cout
?
Sum
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
1
?
0
?
1
?
0
?
1
?
0
?
0
?
1
?
0
?
1
?
1
?
1
?
0
?
1
?
0
?
0
?
0
?
1
?
1
?
0
?
1
?
1
?
0
?
1
?
1
?
0
?
1
?
0
?
1
?
1
?
1
?
1
?
1
?

Design Procedure

Design

Structure
Level

(pass Transistor
, Minority
Gate, TLG Gate)

Sizing the
transistors Width

Applying Low
Power Techniques

Low
Voltage

Sub
threshold

Summary of GP
1
Achievements


Capacitive Inputs

Advantages



Very large fan in capability


Fewer transistors and
interconnections resulting in
small area consumption


Amount of charging and
discharging currents


1.
Minority FA

2.
Threshold logic FA



Minority Full Adder


A minority gate has three inputs and one output and produces
an output value
1
when a minority of input values adders and
selection of the low power design are
1



Minority Full Adder

This design has rail to rail output signals and works properly at low voltages

0

0

1

0

0

1

1

1

0

0

1

1

0

1

0

0

Minority Gate Implementation

Using Capacitor

Using Inverters

Threshold Logic (TLG) Full Adder


Advantages


The
total number of components are
reduced
such
as the number of:


Transistors


Capacitors


The
output signal is regular and has a large voltage
swing




Threshold Logic (TLG) Full Adder

It consists of two
TLG


(TLG)
Implementation

Carry Stage

Sum
Stage


Wired Inverters Minority FA


Wired Inverters Minority FA

CMOS

Inverter Voltage Transfer
Characteristics


The input low voltage (VIL) and the input high voltage
(VIH) are identified in Figure





Case (
1
)
:
V
I

is more than V
IH


There are two cases when PMOS and NMOS operate;


PMOS operating in the saturation region

NMOS operating in the linear region

Drain current for both transistors :

CMOS

Inverter Voltage Transfer
Characteristics


For NMOS transistor VGS = VI and VGS = VO; whereas for
PMOS transistor, VGS = VI
-
VDD and VDS = VO
-
VDD



+

CMOS

Inverter Voltage Transfer
Characteristics

Case (
2
):
As VI less than VIL


NMOS operating in the saturation region

PMOS operating in the linear region

CMOS

Inverter Voltage Transfer
Characteristics

To solve for Vo , VI= VIL

CMOS

Inverter Voltage Transfer
Characteristics

Width Design

NMOS

mobility

length
?
Vdd

(V)

Uo (cm
2
/V.)s

瑯x (c洩

䍯x (F)

V瑨 (V)

W (u洩

L (u洩

W/L

RN (ohm)
?
0.18
u

2

459.0562

4.08
E
-
07

8.46
E
-


0.4452

0.3

0.18

1.666667
?
993.269
?
PMOS

length

Vdd (V)

Uo (cm
2
/V.)s

瑯x (c洩

䍯x (F)

V瑨 (V)

W (u洩

L (u洩

W/L

Rp (ohm)
?
0.18
u

2

109.1231

4.08
E
-
07

8.46
E
-


0.43798

2.2

0.18

12.22222
?
567.3828
?
1
:
01

KR=
10

KR=
20

KR=
45

length
?
VGB
1

VGB
2

VIH

VIL

VIH

VIL

VIH

VIL

0.18
u

1.555677
?
0.933508328
?
1.690688
?
1.192493
?
1.339327
?
0.857918
?
1.46522
?
0.973109
?
Parameter

Values

Voltage

2V

K
R

45

Length

PMOS=NMOS

0.18 µm

Width

PMOS= 1 µm

NMOS= 1.3µm

MIN FA using wired inverters Design
Results

MIN FA Using Wired Inverters



Average Currents & Delay



Propagation Time delay:

T
pLH

(ns)

T
pHL

(ns)

T
p

(ns)

1.4

39.2

20.3

Results

Average


Current

Average

Power

12849nA

25698
nw

Capacitive Inputs

Capacitive Inputs Full Adders
Design


Capacitive Inputs Full Adders Design


Accept multiple inputs signals


Calculates the weighted sum of all input signals


Controls the ON and OFF states of the transistor




The n
-
MOSFET switching ON or OFF depends on whether is greater
than or less than the threshold voltage of the transistor







Capacitive Inputs Full Adders Design


The unique characteristic :


Switching voltage can be varied according to the
selected capacitor values



The key factor is to start with a unit capacitance value


Gate area that for
1.5
mm (edge) standard CMOS process varies
from
580
aF/mm
2

to
620
aF/mm
2

for different runs


Average value has been used which is
596
aF/mm
2





Capacitors Design


Resistors Addition and Design

Most circuit simulators replace the input
coupling capacitors with open circuits
during DC analysis

Capacitive input gate gives a degraded
output level when inputs are not uniform


Solution


Use

a

very

high

resistor

element

as

between

the

capacitive

inputs

gate

and

voltage

inputs

elements


All Low inputs

All High inputs

Not Uniform inputs

Width Design


Parasitic capacitances are in the range of
100
fF
-
400
fF



These capacitances cause rise and fall times of input signals to
increase


It is therefore necessary to resize the transistors by increasing
their W/L ratios


Carry

Stage

Sum Stage


9
/
0.18

PMOS

9
/
0.18

PMOS

16
/
0.18

NMOS

25
/
0.18

NMOS

MIN FA Using Capacitors

Average Currents & Delay

Results

Average


Current

Average

Power

212.309nA

424.618
nw

Propagation Time delay:

T
pLH
(ns)

T
pHL

(ns)

T
p

(ns)

0.634

0.373

0.5

Threshold Logic (TLG)



Threshold Logic (TLG)



Results

Average


Current

Average

Power

15837nA

31674
nw

Propagation Time delay:

T
pLH
(ns)

T
pHL

(
ps
)

T
p

(ns)

2.0234

350.6

1.187

Comparison

Full Adder Structure

1
-
Bit
CMOS

MIN FA

Using Capacitor
?
MIN FA
?
Using Inverters
?
TLG FA

Delay (ns)
?
0.0165

0.5

20.3


1.187

Average Power
(
n
W
)

145.1

424.618

25698

31674


The
1
bit CMOS full Adder Structure has a minimum power
consumption


Sub
-
threshold

1
-
Bit Full Adder Circuit



Using Pass Transistor in structure level design


Sub
-
threshold

Sub
-
threshold behavior of the MOS


As the VTH decreases:


ID leakage


Static power


Circuit instability


ID should fall to zero very quickly after VGS falls
below VTH


S measures by how much VGS has to be reduced for
the drain current to drop by a factor of
10


Applying Sub
-
Threshold
Technique For
1
-
Bit FA


Reduce the voltage of the circuit From
2
to
0.3
V


Design width:


By iteration




Sub
-
Threshold Results

Average

Power

P

?
8.59
pw

Propagation Time delay:

T
pLH
(ns)

T
pHL

(ns)

T
p

(ns)

167.754

90.909

192.33

Sub
-
Threshold Results

Full Adder

1
-
Bit FA

1
-
Bit FA using sub
threshold

Power consumption

145
nw

8.59
pw

Time delay

0.0165
ns

192.33
ns


There is always a tradeoff between power consumption and
the time delay for the full adder.

Project Realization & Performance
Optimization


The

power

in

full

adder

structure

is

minimized

with

the

passage

of

time




Started

with

the

standard

full

adder

structure

(mirror

Full

Adder)

the

power

consumption

was

higher

than

expected




This

led

to

start

concerning

about

the

power

issue

by

looking

forward

new

designs

of

full

adder

structures

that

have

low

power

consumption




As

a

results

of

this

concern,

it

is

founded

today

some

full

adder

structures

that

are

designed

to

consumed

low

power

by

making

them

contain

the

elements

that

help

to

reduce

the

power


Low Power Structure

1.

1
bit CMOS Full Adder is a low power structure that contains a
pass transistor


The pass transistor helped in reducing the power by eliminating the
short circuit currents since there is no voltage source and ground in
it composition


2.
Minority gate Full Adder using the capacitors


Using capacitors will reduce the power consumption because they
replace the transistors, so the amount of the short circuit currents is
reduced







Conclusion



The objective of this project was achieved


The low power full adder design can be achieved by applying
the low power techniques to the structure


Pass transistor and capacitive inputs
elements


Low voltage sources


Sub threshold to any full adder structure


The
1
bit CMOS full Adder Structure is the one that must be
used when searching for low power consumption.




Any Question