Lecture on Flip-Flops

Electronics - Devices

Nov 2, 2013 (4 years and 7 months ago)

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Lecture on Flip
-
Flops

Level
-
Sensitive Flip
-
Flop

Level
-
sensitive flip
-
flop (also called a “latch”)

“Q” changes whenever clock is “high”

CLK

CLK

D

Q

D

Q

CLK

6 Transistors

Level
-
Sensitive Flip
-
Flop

NMOS transistor often
replaced with
“transmission gate”

“Transmission gate”
includes both NMOS and
PMOS transistors because
NMOS good at passing “0”
and PMOS good at
passing “1”

CLK

CLK

D

Q

CLK

CLK

CLK

CLK

D

Q

Transmission

Gate

CLK

CLK

6 Transistors

8 Transistors

Master
-
Slave Edge
-
Triggered Flip
-
Flop

Can connect two level
-
sensitive latches in
Master
-
Slave
configuration to form
edge
-
triggered flip
-
flop

Master

latch “catches” value of “D” at “Q
M
” when CLK is low

Slave

latch causes “Q” to change only at rising edge of CLK

CLK

D

Q

D

Q
M

CLK

Master

Latch

Slave

Latch

Q
M

2 x 8 = 16 Transistors

Q

CLK

Master
-
Slave Edge
-
Triggered Flip
-
Flop

Q

D

CLK

SLAVE

MASTER

CLK

2 x 8 = 16 Transistors

Q
M

More Efficient Master
-
Slave

Edge
-
Triggered Flip
-
Flop

Called a C
2
MOS (Clocked CMOS) design

8 Transistors

Q

D

CLK

CLK

V
DD

GND

CLK

CLK

V
DD

GND

MASTER

SLAVE

Using Logic Gates to Build Flip
-
Flops

From previous slides, you can see that it’s possible to
build an edge
-
triggered flip
-
flop using just 8 transistors

In a conventional “Digital Logic” course, transistor
-
level
flip
-
flop designs are not usually taught

-
flop designs using “cross
-
coupled” logic
gates are usually taught

RS
-
Latch as Cross
-
Coupled NOR Gates

If R = 1, Q resets to 0

If S = 1, Q sets to 1

If RS = 00, no change

RS = 11 is not allowed
oscillation

R

S

Q

Q

0 0

0 1

1 0

1 1

S R

No change

0

1

Undefined

Q

Level
-
Sensitive RS
-
Latch

“Q” only changes when CLK is high (i.e. level
-
sensitive)

When CLK is high, behavior same as RS latch

S

R

Q

Q

CLK

1 0 0

1 0 1

1 1 0

1 1 1

CLK S R

No change

0

1

Undefined

Q

0 X X

No change

Level
-
Sensitive D
-
Latch

Make level
-
sensitive D
-
latch from level
-
sensitive RS
-
latch
by connecting S = D and R = not D

Compared to transistor version

D

Q

Q

CLK

CLK

CLK

D

Q

CLK

CLK

8 Transistors

18 Transistors

Master
-
Slave configuration

Compared to transistor version

Master
-
Slave Edge
-
Triggered Flip
-
Flop

8 Transistors

36 Transistors

GND

GND

Q

D

CLK

CLK

V
DD

CLK

CLK

V
DD

Q

D

CLK

CLK

MASTER

SLAVE

Alternative Edge
-
Triggered Flip
-
Flop

D

Q

Q

CLK

Q

D

CLK

CLK

V
DD

GND

CLK

CLK

V
DD

GND

8 Transistors

24 Transistors

JK Flip
-
Flop from D
-
Latch

Same as RS
-
Latch except “toggle” on 11

D

Latch

CLK

Q

Q

J

K

JK
-
FF

CLK

J

K

Q

1 0 0

1 0 1

1 1 0

1 1 1

CLK J K

No change

0

1

Toggle

Q

0 X X

No change

Toggle Flip
-
Flop from D
-
Latch

Toggles stored value if T = 1 when CLK is high

D

Latch

CLK

Q

T

T
-
FF

CLK

T

Q

1 0

1 1

CLK T

No change

Toggle

Q

0 X

No change