Improving Design Quality by

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Nov 2, 2013 (3 years and 9 months ago)

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1


Improving Design Quality by
Managing Process Variability




ISQED ’09

San Jose, CA


Terry Ma

2

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3


Introduction



Sources of Process Variability



Modeling Process Variability



Design
-
Centric Process Variability Analysis



Design
-
Centric Yield Management



Summary

Outline

4

Moore’s Scaling

Source: IMEC

90nm

65nm

45nm

32nm

22nm

<15nm

Stress engineering implemented at
65nm enables continued scaling

5

What exactly does stress do?

Stress

Band Structure

Mobility

Vt

Leakage

Lattice distortion

Gate

SiGe

Si

NMOS

NiSi

Si
3
N
4

NiSi

Si
3
N
4

stress cap

PMOS

SiGe

SiGe

NiSi

1.2nm

Unlike humans, transistors perform better under stress!

6

If you are a designer….

7

Unfortunately, stress is everywhere…

Each object (diffusion, poly, contact, well edge, …)
contributes to stress!

8

If you look inside a standard cell…

As much as 25% variation in current across a standard cell

0.95

0.8

0.95

0.86

0.98

0.95

0.86

1.03

0.8

0.74

0.74

0.78

0.8

0.74

0.78

0.95

P

N

P
-
Channel

N
-
Channel

Transistor Position

9

Cell context can become a problem too….

Proximity Effect

Typical

Ambit

Lithography

~

1um

Mechanical Stress

~ 2
-
3 um

Well Proximity

~ 1
-
2 um

Adjacent cells

Cell under

analysis

Ambit size

3.7x1.4

2.6x1.0

1.8x0.7

1.3x0.5

5.3x2.0

0.91x0.35

Gate size (um
2
)

32
nm

0.18m
m

0.13m
m

90


65


45


Technology

Minimum gate width for 45nm node is ~0.5 um

10

Design

Manufacturing

Cost

Slip!

Time

Systems

Oops!

The price to pay….

Design

Tapeout

Production

Cost/Change

1X

11


Introduction



Sources of Process Variability



Modeling Process Variability



Design
-
Centric Process Variability Analysis



Design
-
Centric Yield Management



Summary

Outline

12

Sources of Layout Proximity Variation

Litho
Proximity

Mechanical
Stress/Strain

Well Proximity

Effect

Physical Variation

Electrical Variation

Lithographic
Proximity

Shape of poly gate,
diffusion region

Transistor L, W

Mechanical
Stress

Mechanical strain,
defect diffusion

Mobility,
V
th

Well Proximity

Channel Doping

V
th
, Body effect

Electrical Variation

Circuit Variation

Modeling of electrical variation (caused by physical variation)
to account for proximity effects is crucial for
design




13

Lithographic Proximity Variation


Sub
-
wavelength lithography

physical shape variation

Physical shape variation

E
lectrical
variation



CD Variation



Corner Rounding



Drive Current



Leakage



Capacitance



Delay

Transist
or Drain
Current

14

Stress
-
Induced I
on

Variation @ 45nm

Layout A

W=100nm

P2P=120nm

#1 #3 #5

Layout C

#1 #2 #3 #4 #5

0%
5%
10%
15%
20%
25%
1
2
3
4
5
I
on

Variation, %

Transistor Number

PMOS I
on

Sensitivity

A
B
C
~25% I
on

variation even for simple layouts!

(Transistors in Layout A are used for I
on

reference)

Layout B

#1 #2 #3 #4 #5

W=100nm

15



Implant atoms bounce off of photoresist



Extra dopant in channel region changes
V
th
, body effect

Well Proximity Effect



Depends strongly on well / isolation layouts

16

DL

SA

P2P

SDP

WA

H

SDP

jogs

DB

DT

DB

Complex Layout Effects



Jogs (L, H, U, Z, … shapes)




SA (length of diffusion)



DL (longitudinal diffusion spacing)



DT (transverse diffusion spacing)



SDP (active
-
to
-
dummy poly)



P2P (poly space)



WA (DSL and WPE)



DB (distance to boundary)


Poly spacing variation still exists, despite effort to follow
restrictive design rules (RDR)


poly
-
on
-
grid


Active diffusion jogs and corner rounding remain pervasive


17

Added Design Challenges

250nm

180nm

130nm

90nm

65nm

350nm

45nm

32nm

22nm

Timing Closure!

Power

Verification

Signal Integrity

Power!

Verification!

Yield

Power!!

Verification!!

Clocks

Power!!!

Verification!!!

Yield!

Power!!!

Verification!!!!

Yield!!

Variability


18


Introduction



Sources of Process Variability



Modeling Process Variability



Design
-
Centric Process Variability Analysis



Yield Management for Design



Summary

Outline

19

20

How to bridge process and design?

Process

Design

Transistor

Si

STI

STI

Length of
Diffusion


L

s
zz

s


s


W

Layout

21

Designer’s Care
-
about


Everything starts with Spice

Annotated

Spice
Netlist

Accurate Cell Library

Characterization

Spice

Simulations

Critical Path Analysis

Sign
-
off

22

From Physics to Compact Model

Compact
Model

Physical Modeling

23

From Layout to Spice Instance Parameters

Layout

Litho

Stress

WPE

Others

Geometry Processing

Physics
-
based Compact Models
(
m
/
m
ref
,
D
Vth
,
D
L,
D
W, …)

Back
-
annotated

Spice
Instance
Parameters

(
MULU0,
DELVT0,

L, W, …
)

24


Introduction



Sources of Process Variability



Modeling Process Variability



Design
-
Centric Process Variability Analysis



Design
-
Centric Yield Management



Summary

Outline

25

Litho

Contour

Stress

s
xx

s
yy

s
zz

Seismos

LX:

Stress to Electrical

W
eq

L
eq

Seismos

CX:

Contour to Electrical

Layout

Si Calibrated
Stress Model

Visualization

Annotated SPICE
Netlist

HSPICE, HSIM, NanoSim

Design
-
Centric Process Variability Tools

26

Library/Cell Design Flow Drop
-
in

Schematic

Layout

Physical

Verification

Device & RC Extraction

Annotated
Netlist

Spice Simulation

Instance Parameters:
m
eff

s瑨

䱥ff

teff

Seism潳

S瑲ess
M潤el

Tech
䙩汥

27

Model
-
Based Approach Accuracy

0.8
0.9
1
1.1
1.2
1.3
0.8
0.9
1
1.1
1.2
1.3
Modeled
Idlin

Variation

Silicon
Idlin

Variation

Small W

0.8
0.9
1
1.1
1.2
1.3
0.8
0.9
1
1.1
1.2
1.3
Modeled
Idlin

Variation

Silicon
Idlin

Variation

Large W

Desirable

45
o

target

28

Handling tricky layout…

Compressive STIstress pushes

Side of Diffusion edge

Leads to Tensile longitudinal

Stress at bottom edge

In a complex layout, physics
-
based
approach can handle very well the changes
in stress behavior at diffusion corner

29

Visualizing Mobility Variation Across a Cell

strong

weak

30

Doing What
-
if Analysis


Integrated with IC
-
Workbench


Layout editing, with instant in
-
place mobility analysis

O
riginal

nmos

pmos



weaken nmos



enhance pmos

S
hrink
D
iff



enhance nmos



weaken pmos

dummy

dummy

Add
D
ummy

31

Device and Timing Characteristics


Back
-
annotated
netlist

is used
for Spice simulations

% Change ( dense v. sparse)

Params

NMOS

PMOS

Ion


6.0%


16.2%

Ioff


7.0%


16.9%

Delay

-
5.5% (fall)


-
13.9% (rise)

SiGe + STI

3
-
stage

ring oscillator

Dense

Sparse

(
sparse
)

(
dense
)

32

Analyzing Cell Context Effects



Context dependent timing variation can be evaluated to determine



Sensitivity



Distribution



Derating

factor, …

Context Dependent Delay Variation

BUFX4

BUFX4

BUF

BUF

NAND2

NAND2

BUF

BUFX2

NAND2

Filler4

Filler4

NAND2

Filler2

Filler2

NAND2

(a)

(b)

(c)

(d)

(e)

33


Context analysis reveals timing variations, and best
and worst case neighbors

Example: 40nm 24x Inverter

0
5
10
15
20
25
Frequency

t
delay
-
fall
(s
)

0
2
4
6
8
10
12
14
16
18
20
Frequency

t
delay
-
rise
(s
)

100 Random Contexts


2 Timing Arcs

worst

worst

best

best

34



Layout Variation

Typical I
on

variation
range

Typical
V
th

variation
range

Length

of diffusion (LOD) (
SiGe

or STI)

~30%

~50mV

Spacing to adjacent diffusion

~5%

~15mV

Active diffusion

corners

~5%

~15mV

Poly spacing

~15%

~30mV

Poly corner rounding

~5%

~20mV

Well boundary (WPE)/

Dual stress liner (DSL)

~15%

~90mV

Contact

to gate distance

~3%

~10mV

Proximity Variation Summary

35


Introduction



Sources of Process Variability



Modeling Process Variability



Design
-
Centric Process Variability Analysis



Design
-
Centric Yield Exploration



Summary

Outline

36

Statistics and DataMining

Data Visualization / Correlation

Yield Management System

Measurement
and Inspection

Wafer History

Equip. History

FAB

ATPG Tests

DFT Diagnosis

Fail Classification

Arrays Tests

Parametric Test Results

Functional Test Results

TEST

DRC / CAA

Parasitics

STA

LCC /
CMP

EDA

Physical
Design Data

Characterization
Results

Test Engineer

Program Fix

Layout Engineer

Design Fix

Process Engineer

Process Fix

FA Engineer

Faster FA

New Paradigm in Yield Management

Stress

37

Low Yield
Lot

Cell Fail By
Test

Failing Cell
Map

Spatial
Trends

Failing Cells
and Nets

Failing Nets

On Layout

Physical FA

50% Accurate

2
-
3 Days

2
-
3 Weeks

Yield Explorer Automated Flow

Multi
-
Tool Manual Flow






Low Yield
Lot

Physical FA

>90% Accurate


Single Data Bank for yield relevant
data from Design, Fab and Test


An order of magnitude faster
systematic failure localization

Design
-
Centric

Yield Management

38


Introduction



Sources of Process Variability



Modeling Process Variability



Design
-
Centric Process Variability Analysis



Design
-
Centric Yield Exploration



Summary

Outline

39


Stress engineering added to boost transistor
performance at 65nm and below increases process
variability



Interactions between design features and physical
processes result in systematic defects that can degrade
design quality and yield in manufacturing



Design modification made after
tapeout

and in
manufacturing cannot fix everything and is costly



For 45nm and below, design quality and yield can be
improved by properly managing process variability


Summary

40

Predictable Success