An Introduction to VLSI (Very Large Scale Integrated) Circuit Design

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Nov 2, 2013 (3 years and 9 months ago)

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EE141

© Digital Integrated Circuits
2nd

Introduction

An Introduction to VLSI

(Very Large Scale Integrated)

Circuit
Design

Presented at ECE1001

Oct. 12th, 2010


By
Hua

Tang

EE141

© Digital Integrated Circuits
2nd

Introduction

Basic IC circuit component:
MOS transistor

First transistor

Bell Labs, 1948

MOS: Metal Oxide Semiconductor

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© Digital Integrated Circuits
2nd

Introduction


Intel 4004 Micro
-
Processor

1971

1000 transistors

1 MHz operation

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© Digital Integrated Circuits
2nd

Introduction

Intel Pentium (IV) microprocessor

2002

35 Million transistors

1 GHz operation

0.18
μ
m technology

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© Digital Integrated Circuits
2nd

Introduction

Intel Core™2 Duo Processor

2006

>100 Million transistors

2 GHz operation

65
nm technology

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© Digital Integrated Circuits
2nd

Introduction

Intel Core
™2
Quad Processor

2007

>800 Million transistors

2 GHz operation

45
nm technology (

the biggest change in CMOS transistor

technologies in 40 years
)

2009

1 Billion transistors

3.3 GHz operation

23nm technology

EE141

© Digital Integrated Circuits
2nd

Introduction

Moore’s Law



In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.




He made a prediction that
semiconductor technology will double its
effectiveness every 18 months

EE141

© Digital Integrated Circuits
2nd

Introduction

Moore’s law in Microprocessors

4004

8008

8080

8085

8086

286

386

486

Pentium
®

proc

P6

0.001

0.01

0.1

1

10

100

1000

1970

1980

1990

2000

2010

Year

Transistors (MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel

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© Digital Integrated Circuits
2nd

Introduction

Frequency

P6

Pentium
® proc

486

386

286

8086

8085

8080

8008

4004

0.1

1

10

100

1000

10000

1970

1980

1990

2000

2010

Year

Frequency (Mhz)

Lead Microprocessors frequency doubles every 2 years

Doubles every

2 years

Courtesy, Intel

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© Digital Integrated Circuits
2nd

Introduction

Not Only Microprocessors

Analog

Baseband

Digital Baseband

(DSP + MCU
)

Power

Management

Small

Signal RF

Power

RF

Cell Phone


HDTV


PDA


….

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© Digital Integrated Circuits
2nd

Introduction

Design Abstraction Levels

n+

n+

S

G

D

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

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© Digital Integrated Circuits
2nd

Introduction

What is a
MOS Transistor
?

A Switch!

|V

GS

|

An MOS Transistor

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© Digital Integrated Circuits
2nd

Introduction

MOS Transistors
-

Types and Symbols

D

S

G

G

S

D

NMOS

PMOS

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© Digital Integrated Circuits
2nd

Introduction

The CMOS Inverter: A First Glance

V

in

V

out

C

L

V

DD

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© Digital Integrated Circuits
2nd

Introduction

CMOS Inverter

Polysilicon

In

Out

V

DD

GND

PMOS

2
l

Metal 1

NMOS

Contacts

N Well

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© Digital Integrated Circuits
2nd

Introduction

CMOS Inverter

First
-
Order DC Analysis

V

DD

V

DD

V

in

=

V

DD

V

in

=


0

V =0

out

V =V

out

R

n

R

p

DD

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© Digital Integrated Circuits
2nd

Introduction

DC Operation

Voltage Transfer Characteristic

V(x)

V(y)

V

OH

V

OL

V

M



V

OH

V

OL

f

V(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH =
f
(VOL)

VOL =
f
(VOH)

VM =

f
(VM)

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© Digital Integrated Circuits
2nd

Introduction

Mapping between analog and digital signals

V

IL

V

IH

V

in

Slope =
-
1

Slope =
-
1

V

OL

V

OH

V

out



0



V

OL

V

IL

V

IH

V

OH

Undefined

Region



1



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© Digital Integrated Circuits
2nd

Introduction

Definition of Noise Margins

Noise margin high

Noise margin low

V

IH


V

IL

Undefined

Region

"1"

"0"

V

OH


V

OL

NM

H

NM

L

Gate Output

Gate Input

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© Digital Integrated Circuits
2nd

Introduction

Transient Response

t
pLH

t
pHL

The delay

Essentially

determines the

clock speed of the

processor

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© Digital Integrated Circuits
2nd

Introduction

Static
CMOS (Complementary MOS)

V
DD

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are
dual

logic networks

EE141

© Digital Integrated Circuits
2nd

Introduction

NMOS Transistors

in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

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© Digital Integrated Circuits
2nd

Introduction

PMOS Transistors

in Series/Parallel Connection

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© Digital Integrated Circuits
2nd

Introduction

Example Gate: NAND

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2nd

Introduction

Example Gate: NOR

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© Digital Integrated Circuits
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Introduction

Full
-
Adder

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2nd

Introduction

The Binary Adder

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2nd

Introduction

The Ripple
-
Carry Adder

Worst case delay linear with the number of bits

Goal: Make the fastest possible carry path circuit

t
d

=
O(
N
)

t
adder

=
(
N
-
1
)
t
carry

+
t
sum

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© Digital Integrated Circuits
2nd

Introduction

Complimentary Static CMOS Full Adder

28 Transistors

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© Digital Integrated Circuits
2nd

Introduction

Design Metrics


How to evaluate performance of a
digital circuit (gate, block, …)?


Cost


Reliability


Scalability


Speed (delay, operating frequency)


Power dissipation


Energy to perform a function

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© Digital Integrated Circuits
2nd

Introduction

Future Design Challenges


Processor architecture (multiple
-
core;
interconnections)



Semi
-
conductor materials (current
leakage; process variation)



Power consumption (power density;
thermal dissipation)

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© Digital Integrated Circuits
2nd

Introduction

Career in VLSI design

VLSI circuit design and tool development


Intel


IBM


AMD


Cadence


Synopsys


MentorGraphics

....



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© Digital Integrated Circuits
2nd

Introduction

VLSI Design: FFT Butterfly


Widely used in signal
processing


Design Butterfly Unit
for 2
-
point FFT


Components include
multiplier, adder,
subtractor, and data
management

8
-
point FFT composed of 12 butterflies

Image from www.cmlab.csie.ntu.edu.tw/cml/dsp/training/coding/transform/fft.html

By: Spencer Strunic


Matt Webb

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© Digital Integrated Circuits
2nd

Introduction

FFT Butterfly Unit Layout

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© Digital Integrated Circuits
2nd

Introduction


Registers


Store data


Manipulate data


ALU


Select between many different operations to
output


Adder


Adds two 8
-
bit numbers


Multiplier


Multiplies two 8
-
bit numbers


By: Brian Linder


Matt Leines

VLSI Design: 8
-
bit CPU

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© Digital Integrated Circuits
2nd

Introduction

8
-
bit CPU Layout

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© Digital Integrated Circuits
2nd

Introduction

Viterbi Decoder


Cell phones


Dial
-
up modems


Satellite


Deep
-
space
communications


802.11 wireless LANS


Speech recognition
systems


Magnetic disk drives


DNA research

By: Scott Klar


Bibhu Aryal


Ryan Weidemann

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© Digital Integrated Circuits
2nd

Introduction

Final design of 4
-
state decoder

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2nd

Introduction

Full Search Block Matching


Block Matching Algorithm (BMA):


(1) popular motion estimation algorithm


(2) key component of high
-
compression video codecs


(3) used by several standards


n

n

M

S

M

S

p

p

p

p

Current frame (i+1)

Previous frame (i)

Reference block A

Search area

Motion vector

By: Zheng Yi


Chang Hairong

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© Digital Integrated Circuits
2nd

Introduction

Final design (8
×
8 pixel block, search
size 24 pixels)

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© Digital Integrated Circuits
2nd

Introduction

FIR
Filter


FIR


Finite
-
Impulse Response


Involves calculations of finite convolution
sums in discrete
-
time systems


Useful for Digital Signal Processing


Equation
-






x
is the input signal,
h

is the finite impulse
response,
y

is the sum output and
N

is the
order of the filter

By: Craig Bristow


Joliot Chu

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© Digital Integrated Circuits
2nd

Introduction

FIR Filter System Design


x[n]h[k]:

CONT
ROL

Module 1


Control Module

INPUT STORAGE

Module 2


Input Module

COEFFICIENTS

STORAGE

Module 3


Coefficients Module

ARITHMETIC

Module 4


Arithmetic Module

RESULT
S
STORA
GE

Module 5


Results Storage

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© Digital Integrated Circuits
2nd

Introduction

A Delta
-
Sigma Converter for WCDMA

By: Matt
Webb,
Hairong

Chang

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© Digital Integrated Circuits
2nd

Introduction

A speech recognition system

By: Peng Li

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© Digital Integrated Circuits
2nd

Introduction

Contact Information:


Office: MWAH 276

Hour: 2
-
4pm MW

Phone: 726
-
7095

Email:
htang@d.umn.edu

Http: www.d.umn.edu/~htang

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© Digital Integrated Circuits
2nd

Introduction

Build an CPU yourself?

BMOW project (Big Mess of Wires) Material cost: $3,000