# Algorithms of SubCircuit Extraction

Electronics - Devices

Nov 2, 2013 (4 years and 6 months ago)

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Algorithms of SubCircuit Extraction

Presenter: Lei Yang

2002.1

Importance of subcircuit extraction

Introduction of several subcircuit
extraction algorithms

Plan and schedule

Outline

Importance of subcircuit extraction

Introduction of several algorithms

Plan and schedule

Outline

Goal:
To speed up the circuit simulation.

Why ?

Sometimes

circuit

designers

only

want

a

quick

functional

analysis

of

a

circuit

without

necessarily

obtaining

detailed

timing

information
.

Importance of subcircuit extraction

If the circuit is described at transistor level, electrical
simulation may be too lengthy

Importance of subcircuit extraction

However,

if

using

a

subcircuit

extractor,

a

gate

level

of

higer

level

(flip
-
flop,

shift

register)

netlist

is

obtained,

the

simulation

time

could

be

cut

drastically
.

Importance of subcircuit extraction

Importance of subcircuit extraction

Introduction of several subcircuit
extraction algorithms

Plan and schedule

Agenda

The

algorithms

of

extracting

from

the

transistor

level

to

gates

level

and

from

gates

level

to

higher

level

(flip
-
flop)

are

different
.

When

extracting

from

transistor

to

gate

level,

two

kind

of

algorithms

are

considered
:

structure

recognition

algorithm

and

pattern

matching

algorithm

.

When

extracting

from

gate

level

to

higher

level,

only

pattern

matching

algorithm

can

be

used
.

Introduction of several subcircuit extraction algorithms

Summary of all kinds of algorithms

Structure recognition algorithm is based on the
character of MOS circuit.

First,

the

circuit

will

be

divided

into

different

groups,

every

group

is

a

logic

block
.

Secondly,

the

logic

function

of

every

group

will

be

recognized,

such

as

NAND

gates,

NOR

gates,

pass

transistor
.

Introduction of several subcircuit extraction algorithms

Structure Recognition algorithm

Pattern

matching

algorithm

will

transform

the

subcircuit

extraction

problem

into

graph

isomorphism

problem

First,

if

Device

node,

connection

edges

,circuit

network

can

become

into

graph
.

So

the

problem

of

subcircuit

extraction

can

become

graph

isomorphism

---

If

a

given

circuit

block

graph

is

isomorphic

to

a

subgraph

of

a

big

circuit
.

Introduction of several subcircuit extraction algorithms

Pattern matching algorithm

iSPLIT is a extractor from transistor level netlist

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Step 1
---

Initial Subgrouping

1

The

first

transistor

in

the

netlist

is

assigned

group

number

1
,

then

check

the

second

transistor

in

the

netlist

to

see

if

its

drain

or

source

connected

with

transistor

1
,

if

it

is,

then

transistor

2

will

also

be

grouped

into

number

1
;

Then

check

any

other

transistor

in

the

netlist

to

see

if

its

source

or

drain

connected

with

any

transistor

in

group

number

1
,

if

it

is,

it

will

also

grouped

into

number

1
;

2

Then

the

left

transistors

in

the

netlist

are

grouped

into

number
2
,

number
3

..

as

described

in

1
.

Introduction of several subcircuit extraction algorithms

Algorithm 1

Circuit Extractor “iSPLIT”

3 After that, the circuit will be grouped into many disjoint
groups.

Introduction of several subcircuit extraction algorithms

Algorithm 1

Circuit Extractor “iSPLIT”

Step 2
---

Recognition the logic function of every group

1
CMOS

gate

is

comprised

of

two

dual

systems

of

PMOS

and

NMOS

gates(P

system

&

N

system)
.

2
First

check

if

the

number

of

transistors

in

PMOS

and

NMOS

are

equal
.

If

they

are

not

equal,

no

structure

is

recognized
;

3
If

their

numbers

are

equal

and

it

is

one,

then

the

structure

is

an

inverter
;

4
If

the

numbers

are

equal

and

it

is

greater

than

one,

then

having

the

following

step
;

Introduction of several subcircuit extraction algorithms

Algorithm 1

Circuit Extractor “iSPLIT”

5
N

system

is

searched

for

parallel

transistors

(a,

b)
.

Then

check

if

the

corresponding

(a,

b)

is

series

in

P

system
.

If

it

is,

they

are

replaced

by

superdevice

respectively
.

This

superdevice

behave

of

logic

a+b
.

6
Then

P

system

is

searched

for

parallel

transistors
.

After

that,

N

system

will

be

check

if

the

corresponding

transistors

are

series,

then

they

also

replaced

by

a

superdevice
.

7
Then

the

same

process

is

repeated

until

the

P

system

is

replaced

by

a

superdevice,

and

also

N

system

is

replaced

by

a

superdevice
.

At

this

time,

you

can

get

the

logic

function

of

the

group
.

Introduction of several subcircuit extraction algorithms

Algorithm 1

Circuit Extractor “iSPLIT”

The algorithm for NMOS

NMOS has no dual system, and its P system is
replaced by a depletion transistor.

However, the N system is composed of parallel and
series of transistors, using the same method as before, the
logic function of the NMOS can be decided.

End of Algorithm
--

iSPLIT

Introduction of several subcircuit extraction algorithms

Algorithm 1

Circuit Extractor “iSPLIT”

LOGEX

is

also

extracting

from

transistor

level

netlist

to

gate

level

netlist
.

Step

1

Extracting

transistor

branches

1.
Based

on

the

netlist,

transistors

are

combined

to

branches
.

Here

“branch”

is

not

the

same

as

“group”

in

iSPLIT
.

2.
Branch

is

defined

as

a

signal

path,

it

consists

of

transistors

connected

by

their

source/drain

terminals
.

Note

PMOS

transistors

consist

of

PMOS

branch,

and

NMOS

transistors

consist

of

NMOS

branch
.

3.
The

whole

circuit

is

combined

into

three

types

of

branches
:

*

Unidirectional

branches

from

GND

*

Unidirectional

branches

from

VDD

*

Bidirectional

transfer

branches

between

nodes

Introduction of several subcircuit extraction algorithms

Algorithm 2

Circuit Extractor “LOGEX”

4
The above are the three types of branches, every branch has its own
name, the meaning of the name is the following:

Ox: Logic OR with x inputs;

Ax: Logic AND with x inputs;

I: Inverting input (p transistor);

E: Non
-
inverting input (n transistor);

*x: Lasting proceeding element exists x times.

Introduction of several subcircuit extraction algorithms

Algorithm 2

Circuit Extractor “LOGEX”

Step

2

Combining

branches

to

gates

1

The

generated

branches

are

scanned

to

find

if

a

VDD

branch

and

a

GND

branch

are

connected

together
.

2

If

a

VDD

branch

and

a

GND

branch

are

connected

and

they

have

complementary

logic

functions(Ax
-
Ox,Ox
-
Ax,I
-
E,E
-
I)
.

Then

they

are

combined

into

a

real

CMOS

gate
.

End of Algorithm
--

LOGEX

Introduction of several subcircuit extraction algorithms

Algorithm 2

Circuit Extractor “LOGEX”

The character of LIVES

LIVES

is

a

logic

interconnection

verification

system,

not

a

circuit

extraction

program
.

But

some

idea

in

it

is

to

us
.

LIVES

only

handle

E/D

MOS,

did

not

handle

CMOS
.

Every

E/D

MOS

logic

block

did

not

have

dual

system,

its

P

system

will

be

replaced

by

a

pull
-
up

transistor
.

according

to

this

rule,

LIVES

classify

all

the

transistors

in

the

netlist

into

pull
-
up

transistor

and

ordinary

transistors
.

1

pull
-
up

transistor

will

act

the

same

role

as

P

system

in

CMOS

2

ordinary

transistors

will

decide

the

function

of

the

logic

block
.

Introduction of several subcircuit extraction algorithms

Algorithm 3

Logic verification system “LIVES”

Step 1: transistors are merged into groups

1
Because

in

every

E/D

MOS

logic

block,

there

must

be

one

pull
-
up

.

Searching

procedure

starts

from

a

source

node

of

the

picking

up

transistors

one

by

one

until

GND
.

All

the

transistors

form

one

group
.

2
In

the

searching

process,

if

the

node

connects

to

the

gate

of

an

ordinary

transistor,

then

all

transistors

on

the

path

from

the

source

to

the

gate

are

recognized

as

pass

transistors
.

3
This

procedure

is

repeated

for

all

transistors
.

After

that,

transistors

left

behind

and

which

do

not

belong

to

any

groups,

are

considered

as

pass

transistors
.

Introduction of several subcircuit extraction algorithms

Algorithm 3

Logic verification system “LIVES”

Step 2: decide the logic function of every block

1
Making a transistor table. List transistor numbers, drain node
numbers and source node numbers(See the fig in next page).

2
Parallel

path

search
.

Find

a

couple

of

transistors

between

which

both

source

node

numbers

and

drain

node

numbers

are

the

same
.

Then,

those

transistors

are

merged

into

one

transistor
.

This

operation

is

repeated

until

no

such

transistor

pairs

are

left
.

3
Series path search. Almost the same as step2.

4
Step2 and step3 are iterated in turn until only one transistor is
obtained. This procedure is illustrated in next page.

Introduction of several subcircuit extraction algorithms

Algorithm 3

Logic verification system “LIVES”

The following fig shows last page’s step

Introduction of several subcircuit extraction algorithms

Algorithm 3

Logic verification system “LIVES”

All the three program can extract from transistor
level netlist to gate level netlist. They all use the
structure recognition algorithm, and almost have
the same step:

Step 1:

Combine all the transistors in the netlist into
different groups, every group behave one basic gate
cell(For example: inverter, nand, nor, or pass
transistor)

Step2:

In every block, find the parallel and series path
in PMOS system and NMOS system, then recognize
the logic function

Introduction of several subcircuit extraction algorithms

Summery of algorithms in iSPLIT, LOGEX, & LIVES.

Character

of

BLEX

BLEX

use

the

pattern

matching

algorithm,

so

it

can

not

only

extract

from

transistor

level

to

gate

level,

but

also

from

gate

level

to

cell

level

(For

example
:

flip
-
flop)
.

As

stated

before,

because

every

circuit

network

can

become

a

graph,

so

pattern

matching

algorithm

can

transformed

into

a

graph

isomorphism

problem
.

In

the

following,

I

will

use

an

example

to

explain

how

the

BLEX

and

pattern

matching

algorithm

works
.

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

An BLEX example

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

1

Fig(a)

is

a

voltage
-
to
-
current
-
converter,

and

the

converter

circuit

can

be

transformed

into

a

graph
.

2

To

distinguish

the

different

pins

of

one

device,

for

example

‘base’,

‘collector’,

‘emitter’

‘drain’

‘source’

‘gate’,

we

give

them

a

prime

number

to

be

its

weight(See

the

following

table)
:

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

3
Based

on

the

graph,

a

weighted

incidence

matrix

is

generated,

the

element

of

the

matrix

behave

the

weight

number
.

4
From

the

weighted

matrix,

we

can

get

the

weight

of

every

node

and

every

spider(Device

weight

&

Net

weight)
.

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

6

If

here

is

a

subcircuit

block

“current

mirror”,

you

want

to

extract

it

from

the

voltage
-
to
-
current
-
converter
.

First

you

must

get

the

graph

and

the

weight

incidence

matrix

of

the

subcircuit
.

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

Then

you

can

use

the

matching

method

to

see

if

the

subcircuit

weighted

matrix

is

included

in

the

voltage

to

current

converter

weighted

matrix
.

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

Drawback of the BLEX algorithm

1
Though

BLEX

can

extract

all

kinds

of

subcircuit

from

a

big

circuit,

this

algorithm

is

limited

because

it

will

consume

great

deal

of

memory

if

the

circuit

is

big
.

Assuming

that

the

number

of

devices

is

equal

to

the

number

of

nets,

a

circuit

with

1000

devices,

for

example,

has

an

incidence
-
matrix

with

1
E
6

elements,

so

it

is

unaccepted
.

2
However,

the

incidence
-
matrix

is

a

sparse

matrix,

if

we

want

to

use

this

algorithm,

we

must

use

the

-
list

data

structure

to

only

store

the

non
-
zero

elements
.

But

no

one

have

tried

this

kind

of

work
.

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

There

are

some

other

pattern

matching

algorithms,

such

as

one

algorithm

of

Duke

universities,

However,

they

have

the

same

idea

as

BLEX,

they

all

transform

a

subcircuit

problem

to

a

graph

isomorphism
.

Introduction of several subcircuit extraction algorithms

Algorithm 4

Circuit Extractor “BLEX”

Importance of subcircuit extraction

Introduction of several subcircuit
extraction algorithms

Plan and schedule

Agenda

At

the

first

step,

I

want

to

make

a

digital

circuit

extractor
.

To

finish

it,

there

exist

two

phases
:

1
In

the

first

phase,

the

extractor

should

extracts

from

transistors

level

to

gates

level
.

That

is

to

say,

the

extractor

can

extract

the

CMOS

logic

gates

and

pass

transistors,

then

output

one

gate

level

netlist
.

2
In

the

second

phase,

the

extractor

should

extract

some

higher

level

of

cells,

certainly,

the

flip
-
flop

must

be

extracted,

and

other

cells

such

as

shift

register

or

static

RAM

cell

can

also

be

considered
.

Plan

Should

be

farther

discussed

with

professor

Schedule

The End