Network of Excellence

HiPEAC Review

HiPEAC

High
-
Performance Embedded
Architectures and Compilers


IST
–

004408

HiPEAC Review

Gent, 8 November 2006

Network of Excellence

HiPEAC Review

Agenda (i)

From

To

Topic

Speaker

09
:
00


09
:
15


Project

overview

including

Indicators

Mateo

Valero

09
:
15

09
:
45

Implementation

of

pre
-
review

recommendations

Mateo

Valero

09
:
45


10
:
00


Administrative

and

contractual

aspects

including

budget

execution

Pilar

Armas

10
:
00


10
:
15


Achievements

on

Integration

(WP
1
)

including

Website,

calls,

common

equipment

and

staff

Olivier

Temam

10
:
15

10
:
30


Roadmap

Sorin

Cotofana

10
:
30


10
:
50

Coffee

break

10
:
50


10
:
55

Achievements

on

Common

Platforms

(WP
2
)

Per

Stenström

10
:
55


11
:
20

Compilation

Platform

Demonstration

Mike

O’Boyle

11
:
20

11
:
40

Simulation

Platform

Demonstration

Sylvain

Girbal

11
:
40

11
:
45

Achievements

on

Joint

Research

(WP
3
)

Alex

Ramirez

11
:
45

12
:
05

Research Cluster: Cluster on adaptable computing for embedded
applications

Piero

Foglia


12
:
05

12
:
30

Research

Cluster
:

Whole

System

Optimization


Koen

De

Bosschere

12
:
30

14
:
00

Lunch

HiPEAC Review

Agenda (& ii)

From

To

Topic

Speaker

14
:
00

14
:
05

Achievements

on

Spreading

Excellence

(WP
4
)

Koen

De

Bosschere

14
:
05


14
:
20

Management

of

consortium

activities

(WP
5
)

Mateo

Valero

14
:
20

14
:
30

Summary

of

last

year’s

achievements
:

milestones

and

deliverables

Mateo

Valero

14
:
30

14
:
45

General

goals

for

next

period

M
25
-
M
42
,

work

packages

structure,

indicators

and

main

tasks

Mateo

Valero


14
:
45

15
:
00

WP
1

planning

of

the

next

period

M
25
-
M
42

Olivier

Temam

15
:
00

15
:
15

WP
2

planning

of

the

next

period

M
25
-
M
42

Per

Stenström

15
:
15

15
:
30

WP
3

planning

of

the

next

period

M
25
-
M
42

Alex

Ramirez

15
:
30

15
:
45

WP
4

planning

of

the

next

period

M
25
-
M
42

Koen

de

Bosschere

15
:
45

16
:
00

Budget

for

next

period

M
25
-
M
42

Pilar

Armas

16
:
00

16
:
30

Coffee

break

16
:
30

17
:
30

Reviewers

closed

session


17
:
30

18
:
30

Conclusions

and

feedback

–

End

of

review

HiPEAC Review

Project overview

HiPEAC Review

HiPEAC Goals for M13
-
M30

To continue to operate the network

as a virtual centre of excellence in
high
-
performance compilers and
architectures for embedded
processors and to implement

all the tasks foreseen

HiPEAC Review

HiPEAC structure

General Assembly: other members

General Assembly: partners

Coordinator

WP2

Common

platforms

Chalmers

WP3

Joint

research

UPC

WP4

Spreading

excellence

UGent

WP1

Integration

INRIA

WP5 Management

of consortium

activities

UPC

Steering Committee

(SC)

HiPEAC Review

HiPEAC WP

•
WP1 Integration
-

Objectives

–
Updating the HiPEAC intranet and extranet web site

–
Managing calls for collaborations (research clusters,
internships and publications in top conferences

–
Offer seminar talks to all network members via
video
-
conferencing equipment, or via recordings
available via the HiPEAC web site

–
To ensure that members of HiPEAC have access to
computing equipment for performing all required
experimental studies

–
Coordinating full
-
time staff for running the network

–
Defining the roadmap for processor architecture
research and compiler optimizations


•
WP2 Common platforms
-

Objectives


–
Define a modular simulator and work with American
colleagues

–
Evaluate possible infrastructure for compilation
platforms


HiPEAC Review

HiPEAC WP

•
WP3 Joint research
-

Objectives

–
Develop 3 types of research: collaborative research,
industry
-
relevant research, research focused on key
long
-
term issues

–
Stimulate transfer of knowledge between academic
groups and companies

–
Collaborate with American universities within the
NSF/EC
-
IST framework

•

WP4 Spreading excellence
-

Objectives


–
Organize a yearly conference on the topics of interest
Running a HiPEAC Journal to publish state
-
of
-
the
-
art
research on the topics of interest.

–
Running a HiPEAC Newsletter to update network
members on the network activities and results

–
Enticing European researchers in general to publish
in very few top conferences for maximum visibility of
their research work

–
Running the HiPEAC Summer School


HiPEAC Review

HiPEAC WP

•
WP5 Management of the
consortium
-

Objectives

–
Make sure the network runs smoothly

–
Entice active participation of members



HiPEAC Review

Objectives WP1 Integration



Objective 1

Objective 2

Steering
research &
relationship
with
European
industry
Indicator

Objective 3

Fostering joint
architecture &
compiler research
Indicator

Activity /
Objective/
Indicator

Integration
Indicator

Visibility
Indicator

Website

297.556 accesses







Research
Cluster

48 clusters;

Cluster activities: 4
clusters meetings

48 clusters;

12.261 web
accesses

15 clusters
involving
industry
members


16 clusters in joint
compiler
-
architecture
domain

Joint
seminars

6 seminars


126 downloads
seminars



2 talks to/from
industry




Common
computing
equipment

Setup; 64 nodes; 1
sites



Staff

8 fellowships granted



7 internships
granted




Roadmap


Published on the
HiPEAC web site




HiPEAC
label

21 joint publications
with HiPEAC label

165 articles with
HiPEAC label



8 papers with industry
participation


HiPEAC Review

Objectives WP2 & WP3 Jointly
executed research activities



Objective 1

Objective 2

Steering
research &
relationship
with European
industry
Indicator

Objective 3

Fostering joint
architecture &
compiler
research
Indicator

Activity /
Objective/
Indicator

Integration
Indicator

Visibility
Indicator

Simulation
platform

Installation at
test site; 4
platform
meetings


Opening of web
site; publicly
downloadable, 2
tutorials


3 companies at
platform
meetings; 1 joint
cluster activities


Compilation
platform

30 people
contributing to
development


11 public
meetings and
events


4 visits and talks
with companies;
3 joint cluster
activities


Joint
research





21 joint
publications, of
which 8 with
industry; 15
clusters involving
industry
members

21 joint
publications; 16
clusters in joint
compiler
-
architecture
domain



HiPEAC Review

Objectives WP4 Spreading
excellence



Objective 1

Objective 2

Steering
research &
relationship
with European
industry
Indicator

Objective 3

Fostering joint
architecture &
compiler
research
Indicator

Activity /
Objective/In
dicator

Integration
indicator

Visibility
Indicator

HiPEAC
Conference

84
submissions &
64 attendance
HiPEAC
members


37 attendance of
non
-
HiPEAC
members


1 out of 2 talks
by industry
researchers &
non
-
architecture

/compiler
community
researchers

1 HiPEAC
members joint
articles; 3
articles of
members with
non
-
members


HiPEAC
Journal



14 submissions;
112 downloads (full
or article); 10
published articles




3 out of 10

HiPEAC
Newsletter



700 issues






Stimulating
publication
in top
conferences



19 articles in top
conferences


Summer
School

135

members

75

non
-
members

29 persons from
9 companies



HiPEAC Review

Implementation of pre
-
review
recommendations

HiPEAC Review

Recommendation 1

Industry Involvement

Encourage

a

more

direct

involvement

in

the

research

from

industrial

partners,

in

particular

application
-
level

companies

operating

in

the

embedded

market,

to

improve

industry

involvement

into

the

project

to

reach

the

level

expressed

in

the

Technical

Annex

.


•
Thales has been actively involved in HiPEAC activities

–
On
-
Going discussions with Thales for direct involvement

–
Topics of interest: software
-
defined radio, defense
applications

•
Significant indirect feedback on embedded applications
by partner companies; application
-
level companies are
their customers (Nokia, Thales,…)

•
Nokia already involved in joint European project (started
June 1st), and will now be asked to join HiPEAC

•
We keep seeking contacts with application
-
level
companies

HiPEAC Review

Access to applications:

IPR barriers

Embedded product manufacturers

complete products/applications

(sub
-
)system solutions

technology exploration

(methodologies, tools, architectures…)

Product divisions of solution providers

Industrial and academic research teams

requirements,

algorithm outlines

requirements,

design needs

system
-
level

components

proposed methods,

tools, designs

HiPEAC scope

IPR barrier 1: product vs. subsystem

benchmarks?

IPR barrier 2: subsystem vs. research

benchmarks?

HiPEAC Review

Recommendation 1

Industry Involvement

The

presence

of

companies

as

active

members

in

the

research

clusters

must

be

further

improved

as

well

as

the

networking

of

clusters
.


Industry
-
focused

actions

–
Companies part of Steering Committee

–
Companies influence cluster selection

–
Company internships

–
Clusters meetings at company sites

–
2 HiPEAC Industry Workshops

•
ST, Grenoble, France, May 2006

•
NXP, Eindhoven, The Netherlands, October 2006

–
New member companies: ACE, Xyratex

•
Increasing participations of Intel, ARC, Xilinx

•
In cluster call announcement, clear focus towards
companies

–
«

Cluster proposals are now evaluated based on industry
-
relevance criteria in addition to research criteria; industry
SC members have a significant say in cluster selection

»

HiPEAC Review

Recommendation 1

Industry Involvement

•
1st year: 32 clusters, 4 with industry

•
2
nd

year: 48 clusters, 15 with industry


1.
Adaptable Computers for Embedded Applications 2 (STMicro)

2.
Investigation of real
-
time capable embedded SMT processor techniques

(Infineon)

3.
Scalable System Architectures (#3) (Simula Research Labotatory, XYRATEX)

4.
Whole System Optimization (IBM)

5.
Collaboration on Multithreading processor design (Infineon)

6.
Identification and Specialization of Frequent Patterns of Computations in Programs
(Philips, ARM)

7.
GCC research platform cluster (IBM, Philips)

8.
Automatic Parallelization for Embedded Parallel Architectures (IBM, Philips)

9.
Embedded Tiled Architectures (ST)

10.
Machine Learning Techniques for Adaptive Optimization (IBM, STMicro)

11.
Simulation and Compilation Platforms Cluster (IBM, STMicro, ARM, Philips Research)

12.
Applications enabling the exploitation of heterogeneous architectures for the
embedded market (IBM)

13.
Ahead of Time Analysis and Optimizations for Just In Time Compilation (STMicro)

14.
Exploring optimization techniques and runtime code selection mechanisms for
heterogeneous systems (IBM, STMicro)

15.
Optimizing High Performance Loops for Embedded Processors (IBM, STMicro)


HiPEAC Review

Recommendation 1

Industry Involvement

•
Networking:

–
Thematic

workshop organized together with
clusters meeting

•
Programming models

•
Simulation

•
…

HiPEAC Review

Recommendation 1

Industry Involvement

Existing

research

clusters

should

be

analysed

to

highlight

which

embedded

applications

stand

to

benefit

more

from

the

research

work,

and

in

what

timeframe

(short,

mid

and

long
-
term)
.

This

should

be

part

of

the

submission

form

for

next

calls

and

the

selection

procedure

should

take

this

into

account
.

Also,

direct

embedded

computing

topics

must

have

priority

in

developing

new

research

clusters
.

•
After

consulting

with

companies,

they

consider

our

research

as

enabling

technologies

and

should

cover

a

very

wide

range

of

applications

HiPEAC Review

Recommendation 1

Industry Involvement

Further

support

the

organization

of

industrial

workshops

in

each

company

to

show

not

only

technology

advances,

but

also

the

benefits

of

the

research

on

the

embedded

market
.

More

in

general,

we

continue

to

strongly

recommend

increasing

joint

research

developments,

including

published

papers

between

partners,

especially

between

academic

and

industrial

partners


•
Have

organized

a

second

industry

workshop

•
Will

keep

organizing

industry

workshops

at

clusters

meetings

•
STREPs

evolved

from

clusters,

and

include

joint

industry/academia

research

HiPEAC Review

Recommendation 2

Joint architecture/compiler

The

joint

research

on

architecture

and

compilers

should

be

intensified

by

increasing

the

number

of

joint

research

clusters

and,

more

in

general,

by

fostering

a

tight

cooperation

between

the

simulation

and

compilation

platforms
.


•
We

are

already

doing

combined

research

•
Not

enough

resources

to

achieve

platform

cooperation

within

the

4

years

of

HiPEAC


It

is

necessary

to

report

better

achievements

focused

on

both

compilation

and

simulation

frameworks

and,

in

this

respect,

to

offer

a

demonstration

of

the

two

platforms

work

during

the

next

review

in

Ghent

•
See

demos

HiPEAC Review

Recommendation 3

Delivery

For

the

next

review

the

HiPEAC

Consortium

is

strongly

requested

to

submit

the

deliverables

package

to

the

reviewers

at

least

two

weeks

before

the

date

of

the

review

meeting


•
The reports were submitted on time


HiPEAC Review

Recommendation 4

Members

To

include

in

the

new

version

of

the

technical

annex

the

detailed

procedure,

not

only

to

engage

new

members

to

the

HiPEAC

Consortium,

but

also

to

drop

out

some

members

not

contributing

to

the

project

objectives
.


•
Work in progress

•
The mechanism will be included in the
consortium agreement by means of an
amendment

HiPEAC Review

Recommendation 5

Roadmap

Although

a

big

effort

was

recognized

by

the

reviewers

to

produce

the

present

version

of

the

roadmap,

the

HiPEAC

Consortium

is

requested

to

produce

a

new

version

of

the

roadmap

deliverable

by

the

beginning

of

October

2006


•
Updated

version

of

the

roadmap

•
Will

write

a

research
-
focused

part

II

of

the

roadmap

•
Topics

–
Single
-
Core (
André?
, Alex,
Mateo, Theo)

–
Multi
-
Core (
Per
, Olivier, Piero,
Mateo, Alex)

–
Simulation (
Olivier
, Lieven, Per)

–
On
-
Chip networks (
Dionisis
,
Jose, Manolis)

–
Reconfigurable computing
(
Georgi
?, Nacho, Dionisis, Theo,
Per, Wayne Luk)

–
Compilers (
Mike
, Albert, Olivier,
Koen)

–
Programming models (
Xavier
,
Olivier, Nacho, Angelos)

–
Benchmarking & applications
(
Alex
, Koen)

–
Run
-
Time system (
Nacho
, Koen,
Olivier)

–
Real
-
Time (
Pascal
, Theo, Fran)

–
Integration (
Koen
)

•
1 to 2 pages per topic

•
Schedule:

–
Dec. 1st: First draft

–
Dec. 8th: Integration

–
Jan. 1st: Feedbacks from fellow
experts

–
Jan. 8th: Final version


HiPEAC Review

•
First, we suggest to add into the Introduction the description of the

methodology that has been used to build a credible roadmap and to maintain

it updated (as required in the previous review too). We have also to

consider that most of the sources used for the roadmap have been published

in 2005 and they can quickly become obsolete.


–
We added a new paragraph on the roadmap methodology. There are also a lot of
references

from sources

of 2006.


•
The reviewers appreciate the new Chapter 3 focused on market research that

was introduced according to the reviewers recommendations. The roadmap

marketing section is especially focused on to the industry. The chapter is

well focused on embedded hardware market but, however, it might be improved

on embedded software market. In this sense, some details related to

compilers and simulation platforms’ roadmap would be useful (being this

topic one of the main HiPEAC objectives). For example, concerning compilers,

the focus should not be on the compiler niche market but more importantly on

the impact that advances in compilers could have on the embedded

applications market.


–
Unfortunately, we don’t have this information about the compiler market.

Recommendation 5

Roadmap

HiPEAC Review

•
The reviewers also recommend including in the final version of the roadmap

a topic on benchmarking (as already required after the previous review).

This topic might be inserted before paragraph 7.10 page 87 entitled

“Applications”. In particular, domain specific benchmarks such as for

multimedia, real
-
time automotive, network processors, signal processing,

consumer devices, office automation, etc could be analysed. The reviewers

suggest referring to the keynote presentation of Markus Levy, the President

of EEMBC, at the HiPEAC 2005 Conference. Especially EEMBC further projects, presented in Levy’s
presentation, might be useful in developing benchmarks’ future trends. This is very important
taking into account that embedded applications characteristics aren’t published at this moment,
and, therefore, only better understanding embedded benchmarks might give a

realistic idea about the embedded applications’ present and future.


–
We moved the section of the application to a new chapter. Mark has not replied but we are still trying to find
some more information about the future of the applications/benchmarks.


•
The reviewers recommend to point out at the end of each chapter, the

HiPEAC original contributions and opinions on the roadmap, based on the

valuable experience of HiPEAC members in researching different embedded

systems domains (compilers, simulation frames, microarchitectures, etc.).

Perhaps it would be useful to collect from each HiPEAC member some original

opinions, based on his own work and experience.



–
We made a plan to solve this by
writing a research
-
focused part II of the roadmap
. The first version will be
available by January 8 2007.

Recommendation 5

Roadmap

HiPEAC Review

•
The reviewers also recommend to try to unify the description style of each

chapter, since the chapters seem quite heterogeneous to each others.


–
We unified the form of all the chapters and the sub
-
chapters to make the whole document
consistent.


•
The HiPEAC consortium should agree whether the term “digital logic” (one

of the 4 sub
-
systems of an embedded system, see page 33 of the Roadmap

rev.2) is the most appropriate or whether it should be replaced

(despite reference 7 use this term). Rather than “digital logic” we should

suggest “digital (sub
-
)system”, taking into account that it contain digital

processing elements including memory.


–
We changed to digital sub
-
systems all over the place.


•
Chapter 5 (EDA Roadmap for embedded systems) mainly refers to MEDEA+ EDA
ROADMAP published on 2003, while on web there is an updated MEDEA+ EDA
ROADMAP Version 5 published on July 2005. The review recommend to update
Chapter 5 consequently.


–
We have updated to MEDEA 2005.

Recommendation 5

Roadmap

HiPEAC Review

•
Chapter 6 (Embedded Computing Roadmap) mainly refers to [43]: Jim
Turley, "Survey says: software tools more important than chips",
Embedded System Design, 2005, but this paper contains a survey based
on interviewing a mix of programmers and engineers in the embedded
fields. In our opinion it is a debatable source. Moreover, in the roadmap it
is not cited properly. Let us consider for example Figure 6.2. The
roadmap cites: " currently half of the embedded design (52.4%) use
single processors etc", while in the cited paper referring to the same
figure the author says: "barely half (52.4%) said they're using only a
single processor in their current project". The review recommend to
update Chapter 6 consequently.


–
Fixed as recommended.


•
At Reference 7, the other two authors, Faraboschi and Young, were
omitted.



–
Fixed.

Recommendation 5

Roadmap

HiPEAC Review

•
Paragraph “Applications and Trends”, page 67 is more focused on
architectures characteristics (CMP) rather than on applications’ trends.
Therefore, we suggest correspondingly changing the paragraph’s title and

moving all what’s related to applications in this paragraph (few things)
into paragraph 7.10, page 87, entitled “Applications”.


–
We changed the title but as this section is very close to multiprocessing we
believe it is better to stay in this section.


•
A Glossary, giving pragmatic definitions to the most used terms in

embedded computing, might be also very useful.


–
I added a glossary at the end of the document citing the most important terms.


•
Additionally, we extended the section dedicated to compilers.

Recommendation 5

Roadmap

HiPEAC Review

Recommendation 6

Compilation platform

Since two compilation platforms (GCC and
CoSy) have been selected, the reviewers
recommend to exploit the research on
both of these platforms in a synergetic
manner to achieve the integration goals
of the HiPEAC project


•
Research

is

very

different

–
GCC

is

about

vectorization

&

parallelization,

machine
-
learning
-
based

adaptation

–
CoSy

is

about

instruction

selection

for

ASIP

design,

and

co
-
design


•
Due

to

IP

restrictions,

code

sharing

is

impossible

HiPEAC Review

Recommendation 7

Papers

The reviewers recommend publishing papers
especially in ISI Thomson journals with high
ranks
-

JRK and impact factors
-

IF (IEEE
Transactions, ACM Transactions, Info Techn.
R&D, IBM J. R&D, etc.). These papers would be
separately reported, with the corresponding
scientometric parameters (JRK, IF), as they
result from accessing specific databases like ISI
Thomson, DBLP, CiteSeer, etc
.


•
Our

domain

works

differently

•
Full

consensus

in

our

community

that

conferences

are

key

HiPEAC Review

Recommendation 8

Journal

The

reviewers

recommend

to

the

Consortium

to

collaborate

with

Springer

in

order

to

be

sure

that

HiPEAC

Journal

already

is

or

it

will

be

included

in

the

ISI

Philadelphia

Thomson

recognised

journals

list

as

soon

as

possible
.


•
Published

in

LNCS

•
LNCS

is

already

ISI

Thomson

•
So

HiPEAC

Journal

is

ISI

Thomson


HiPEAC Review

Recommendation 9

ARTEMIS

Increase

the

visibility

and

the

link

with

Artemis,

going

beyond

the

current

general

involvement

to

linking

directly

to

each

relevant

company

active

in

Artemis,

for

instance

through

the

industrial

workshops

or

seminars
.


•
Joint

Artemis
-
HiPEAC

event

at

IST

2006

Helsinki


–
Discuss

future

MPSoCs

–
Maybe

panel

headed

by

Per



HiPEAC Review

Administrative and contractual
aspects including budget execution


HiPEAC Review

Administrative aspects

•
15 HiPEAC partners (after Virtutech’s
withdrawal)

•
Consortium Agreement:

–
Second Amendment to the Consortium Agreement in
order to include all industry partners. December 2005

–
Third Amendment in progress (clarifies process for
accepting/dropping members)

•
Distribution of funds

–
UPC receives the funding from EC and distributes it to
the partner responsible for the task according to the
DoW

–

Funding for research clusters, fellowships, internships
and publications on top conferences is allocated
according to call for collaborations

HiPEAC Review

Funding (i)

•
Who has access to funding?

–
Part of the funding is not
a priori

distributed;

–
Funding is distributed through calls for
collaborations:

•
research clusters

•
publication in top conferences

•
internships

–
Calls open to HiPEAC community

•
Members have rights & duties

–
The right to benefit from the network funding
and activities

–
The duty to actively participate to network
activities and help promote the network

HiPEAC Review

Calls results

Collaboration title

Total
€

fellow

m

Members participating

Adaptive Prediction Techniques for branching,
prefetching, and coherence

4.000

0

6

Chalmers, UPatras

Power
-
efficient Cache technologies

32.000

24.000

12

Uppsala, UPatras

Kilo
-
instruction Multiprocessors

10.000

0

3

UPC, Chalmers, UPV

Kilo
-
instruction Multiprocessors

(extension)

50.000

13.200

Chalmers, UPC, Ucantabria


Scalable System Architectures

10.000

0

12

Forth, UPC, UPV, UCrete, Simula,
Uppsala, PdT, UCantabria, Royalinst

Scalable System Architectures (extension)


30.000


0

Simula, Royalinst, Uppsala,Xyratex,
FORTH,UPV,UPC,TUD,Ucantabria,
Ucrete


Accurate and Complexity
-
Effective Coherence
Predictors

7.880

0

6

Chalmers, UZaragoza

Intelligent Checkpointing for Kilo
-
instruction
Processors

20.000

12.000

12

UPC, UAthens

Activation/Deactivation of Overiding Predictors in
High Performance Processors for Increased Power
-
Efficiency

4.500

0

12

UAthens, UCrete, UCyprus

Confidence estimation and fetch gating using
state
-
of
-
the
-
art branch predictors

4.000

0

12

INRIA, UGent

Scalable System Architectures (extension)

5.000

0

3

Forth, UPC, UPV, UCrete, Simula,
Uppsala, PdT, UCantabria, Royalinst

Managing Caches for SMT and CMP

16.000

0

12

UEDIN, Uppsala, Upatras


Reconfigurable Computing


25.000

TUD,UAU,UPC,Upatras, ImperialCol,
Ukarlsruhe, Ucrete,INESC
-
ID, Ugent


HiPEAC Review

Calls results

Collaboration title

Total
€

Fellow

m

Members participating

System Level Performance/Power Evaluation of
Stream Processing Embedded Systems

1.800

0

3

UAmsterdam

Collaboration on vector processing research

6.000

0

3

UPC, TUD

Collaboration on Multithreading processor design

6.000

0

3

UPC, CNRS, UAU

Investigation of real
-
time capable embedded SMT
processor techniques

(extension)

48.900

13.200

UPC, UAU, CNRS, Infineon


Adaptable Computers for Embedded Applications

5.000

0

12

UP, Chalmers, Usiena

Adaptable Computers for Embedded Applications

2

30.000

20.000

Chalmers,UP,Upatras,Usiena,ST,TUD


Automatic synthesis of Application Specific
Instruction
-
set Processors

7.000

0

6

TUD, Inesc
-
ID

Embedded system miniaturization and power
autonomy

6.000

0

9

UPC, UCrete

Reconfigurable SoC with multithreded processor
core extending cluster: Collaboration on
Multithreading processor desig

13.900

12.500

3

UAU, TUD, Infineon

Fellowship for Adaptable Computers for Embedded
Applications

16.000

12.000

12

Chalmers, UP, USiena

Advanced Hardware Cache Monitors and Their
Application to Reconfigurable Cache Architectures


4.000

12

UEDIN, Karlsruhe


Combined Hardware/Software Approach to
Coherence for Embedded Chip Multiprocessors


7.300

12

UEDIN, Chalmers


NSF (Rutgers)
-

HiPEAC Collaboration on
Cooperative Embedded Computing


16.800

10.800

Ucrete, UPC, Ucyprus


Value
-
driven Embedded Processors


26.400

12.000

UPC, UEDIN


HiPEAC Review

Calls results

Collaboration title

Total
€

of which
fellow

m

Members participating

Process Migration in Multi
-
Core Processors and
its application to the Power Density Problem

17.150

13.200

12

Inria, UCyprus

Energy
-
efficient single
-
core processor design

4.000

0

3

UPV, UPatras

Multicore Embedded System Architecture

8.000

0

10

TUD, UP, USiena

CMPs
-
based network and storage I/O
subsystems

8.000

0

12

UCrete, TUD, UAmsterdam

Embedded Tiled Architectures


10.000

12

Usiena, UP, Upatras, UPC,
INRIA, UEDIN, ST


Simulation Tools for On Chip SMT Multiprocessors

10.000

0

6

UPC, Chalmers

Statistical simulation techniques for uniprocessor
and multiprocessor systems

8.000

0

6

UGent, INRIA, Uppsala

Adaptive Optimisation

51.120

42.600

12

UEDIN, Inria

RWTH Aachen contribution to compiler and
simulation platforms

3.000

0

6

UEDIN, Inria, TUD, RWTH,
Dortmund

System
-
level Software Optimization

4.000

0

3

UPC, UGent

Co
-
exploration of embedded processor
architectures and code transformations

10.500

0

24

RWTH, UEDIN

System
-
level Software Optimization (Extension)

15.600

6.600

6

UGent, UPC

GCC research platform cluster

18.000

0

6

INRIA, IBM, Philips, Imperial,
UPC, UEDIN, CNRS

Automatic Parallelization for Embedded Parallel
Architectures


16.000

12

IBM, UEDIN, INRIA, Philips,
UPC


Whole System Optimization


46.800

21.600

UEDIN, Ugent, UPC, IBM


Simulation and Compilation Platforms Cluster


67.600

60.000

Chalmers, UEDIN, UPC, INRIA,
Ugent, Ucantabria, IBM,
Philips, ST, ARM

HiPEAC Review

Calls results

Collaboration title

Total
granted

Of which
Fellowship

duratio
n

Members participating

Identification and Specialization of Frequent
Patterns of Computations in Programs

4.000

0

6

UCyprus, Philips, INRIA, ARM,
CNRS, TUD

Applying Self
-
x
-
techniques to Enhance Robustness
of Networked Embedded Systems

4.000

0

12

UAU, UPatras, UKarlsruhe

Fellowship for S. Kavvadias (interprocessor
communication mechanisms)


18.000

12.000

12

UPC, Ucreta, UPV, TUD, FORTH

Machine Learning Techniques for Adaptive
Optimization


no funding
requested

no funding
requested

12

INRIA, IBM, ST, UEDIN


Publications at conferences

Travel funding for INFOCOM

2.000

0

1

UPatras

Presentation of an article at ISCA symposium

2.340

0

1

INRIA

Presentation of ICS paper

1.400

0

1

UPC

Presentation of ICS paper

1.400

0

1

UPC

Ph.D. student funding for DAC 2005 trip

1.800

0

1

RWTH

Presentation of LCTES paper

1.450

0

1

UGent

Paper presentation at HPCA (Austin, Texas)


1.910

0

1

UPC

Travel funding for ISLPED 2005


2.100

0

1

UPatras

Total Publication at conferences

14.400







Total funds committed accepted proposals

751.650
€

285.700
€

HiPEAC Review

Calls results (Sep. 2006)

Collaboration title

Total
granted

Of which
fellowship

Members
participating

Applications enabling the exploitation of heterogeneous architectures
for the embedded market

33600

21600

IBM, University of
Crete, UPC

Ahead of Time Analysis and Optimizations for Just In Time Compilation

15500

3000

INRIA, ST, UEDIN

Co
-
Synthesis of Instruction Set Extensions and Advanced Optimising
Compilers for Configurable Embedded Processors

10000

0

UEDIN, RWTH,
Imperial

Core Working Sets and Bypass: Towards Highly Efficient Memory
Hierarchies

8000

0

Hebrew, Chalmers

Exploring optimization techniques and runtime code selection
mechanisms for heterogeneous systems

37600

21600

UPC, IBM, ST,
INRIA

Modular & Transaction
-
Level Full
-
System Multi
-
Processor Simulation

7020

0

UPC, INRIA

NSF/IST Collaboration: Univ. of Patras & Princeton

6000

0

Upatras

Optimizing High Performance Loops for Embedded Processors

14400

8400

INRIA, IBM, ST

Statistical Simulation of Multicomputer Systems and Analytical
Performance Modeling

20400

0

UPC, Ugent

The FlexSoC Approach Towards Reconfigurable Computing

12000

0

Chalmers

Total clusters accepted September 2006

164520

54600

Publications at conferences

Paper presentation at CASES (Seoul, Korea)

2500

INRIA

Paper presentation at PACT

2000

UPC

Presentation of ASPLOS paper

1500

Ugent

Presentation of ICS paper

2500

Ugent

Presentation of ICS paper
--

bis

2500

Ugent

Presentation of PACT paper

1500

Ugent

Total publications accepted September 2006

12500

HiPEAC Review

Budget for M13
-
30 (i)

Funded items will be:


Integrating activities:

•
Website
: cost of HiPEAC website server and registration cost for the hipeac.net

•
Research clusters:

costs of travelling for research cluster purposes; travelling to
top conferences of the author of a HiPEAC labeled paper, including registration cost;
and General Assembly (GA) travelling.

•
Joint seminars
: unexpected costs in the development of the joint seminars
activity, such as equipment, telephone charges, etc.

•
Permanent staff
: The cost of hiring staff members to run and coordinate the
network activities; this includes the administrative staff and the support engineer

•
Roadmap
: cost of hiring staff to elaborate the roadmap


Jointly executed research activities:

•
Platform development and integration
: cost of hiring an engineer to develop the
simulation and compilation platforms, and to integrate those parts developed by
doctoral students at the member institutions


•
Internships
: cost of summer internships in a HiPEAC European company

•
Doctoral degree fellowships
: the HiPEAC steering committee defines topics of
interest in terms of advanced and joint research, and provides funding for PhD
students doing research on those topics. This item shows the total amount for those
fellowships each year



HiPEAC Review

Budget for M13
-
30 (& ii)

Spreading of excellence activities:

•
Conference:

organization costs of the HiPEAC conference and scholarships for
selected HiPEAC students to attend

•
Newsletter:
publication costs of the HiPEAC newsletter


•
Summer School (Courses)
: organization expenses of the HiPEAC summer
school.This includes subcontracting of the facilities where the Summer School takes
place

and HiPEAC scholarships for students


Consortium management activities

•
Audit certificates

•
Steering committee meetings
: cost of travelling of the SC


HiPEAC Review

Budget and actual costs

Type of expenditure

Allocated

Actual costs
€

Spent %

Y2

Remaining

from budget

Period 1

Period 2

Total

Personnel costs

7.870.926

1.611.590

1.861.077

3.472.666

44%

4.398.259

Overhead

3.576.977

877.504

1.027.613

1.905.116

53%

1.671.860

Website

7.275

0

0

0

0%

7.275

Research clusters (travel)

909.749

45.755

142.657

188.412

21%

721.337

Joint seminars

1.594

0

0

0

0%

1.594

Permanent staff (within personnel)

467.438

28.387

79.079

107.466

23%

359.972

Roadmap (within personnel)

160.697

10.697

48.909

59.606

37%

101.091

Platform development/integration
(within personnel)

231.000

0

31.474

31.474

14%

199.526

Internships

240.000

0

0

0

0%

240.000

Doctor degree fellowships (within
personnel)

1.102.900

34.761

139.450

174.211

16%

928.689

Conference + Journal + Newsletter

111.000

8.295

20.396

28.690

26%

82.310

Publication in top conferences

2.191

2.191

0

2.191

0%

1

Courses (summer school)

412.000

36.110

204.399

240.509

58%

171.491

Audit certificate

21.880

0

3.145

3.145

14%

18.735

Steering commitee meeting (includes
Ind.Adv.Board)

193.151

37.645

41.117

78.762

41%

114.389

Industrial Advisory board

19.125

0

0

0%

19.125

Academic Advisor Board (GA)

20.000

6.804

6.804

0%

13.196

Total Costs

15.347.902

2.625.893

3.300.403

5.926.295

39%

9.421.607

HiPEAC Review

Summary total expenses

(funded cost categories)

Y1
-

Budget
DoW pg.62

Y2
-

Budget
DoW pg.60

Spent
-

Form
C Y1

Spent
-

Form
C Y2

Total Spent
Form C

Integrating activities











Website


1.000

2.000
€


-



-



-


Research Clusters
-

Travel


200.000

200.000
€

45.755

142.657

188.412

Joint seminars


1.250




-



-



-


Permanent staff


72.500

125.000
€

28.387

79.079

107.466

Roadmap


2.500

50.000
€

10.697


48.909

59.606

Jointly executed research activities











Platform development / integration


40.000

60.000
€


-


31.474

31.474

Internships


48.000

80.000
€


-



-



-


Doctor degree fellowships


373.000

210.000
€

34.761

139.450

174.211

Spreading of excellence activities











Conference



20.000
€

8.295

9.918

18.212

Newsletter

(above)

12.000
€

(above)

10.478

10.478

Publication in Top Conferences


50.000

(within clusters)

2.191

within travel

2.191

Courses


81.250

103.000
€

35.120

202.419

237.539

Consortium Management activities











Audit certificates


18.000

7.000
€


-


3.145

3.145

Steering Committee meeting


30.000

45.000
€

37.645

41.117

78.762

Industrial Advisor Board


15.000

(within SC)


-



-



-


Academic Advisor Board


20.000

(within Travel)

6.804

within travel

6.804

Overhead (not budgeted)

(above)

19.901

52.725

72.626

Total

952.500
€

914.000
€

229.555
€

761.371
€

990.926
€

HiPEAC Review

Person
-
months













TOTALS
(permanent &
non
-
permanent
p
-
m)

Of which
permanent
p
-
m (only AC
members)

Workpackage 1:


Integration

Actual WP total:

38

6

Planned WP total:

52



Workpackage 2:


Common platforms

Actual WP total:

17

8

Planned WP total:

28



Workpackage 3:


Joint research

Actual WP total:

395

70

Planned WP total:

532



Workpackage 4:


Spreading excellence

Actual WP total:

46

9

Planned WP total:

38



Workpackage 5:


Management of consortium

Actual WP total:

18

5

Planned WP total:

12



Total Project Person
-
month
(planned for 18 months)

Actual total:

512

98

Planned Total:

662



HiPEAC Review

Funds committed in clusters

•
The funds committed by means of call for
collaborations are:



Y1

Y2

Y3

Total

Clusters + publications
in top conferences

211.940
€

254.010
€

122.420
€

588.370
€

Fellowships

122.900
€

162.800
€

54.600
€

340.300
€

Total calls

334.840
€

416.810
€

177.020
€

928.670
€

HiPEAC Review

Discrepancy in Allocated/Spent
Funding

•
Analysis

–
Today’s snapshot

–
Conservative spending, partly due to hub
meetings

–
Timeline for allocation of resources

–
Accounting delays

•
Solutions to be implemented

–
Step up fellowships for long stays: travel
grants

–
Block budget distribution for hub meetings


HiPEAC Review

HiPEAC Staff

HiPEAC Review

HiPEAC Staff

•
Support staff

–
Pilar Armas

•
Administrative, contractual and financial issues

•
Assistant of coordinator

–
Sylvain Girbal

•
Platform engineer

–
Christopher Kachris


•
Roadmap

–
Thomas van Parys

•
Technical support for multiple activities (conference,
summer school, meetings,…)

•
Web site

•
Newsletter

•
Soon: remote collaboration tools,…

•
Fellows (clusters)

–
15 fellowships granted through calls for collaborations
(plus 4 more in Y3 and 14 travel grants)

HiPEAC Review

WP1
-

Integration

HiPEAC Review

Web Site

•
Rapidly growing number of registered users (440 users)

•
Intranet vs. Extranet

–
View and access rights based on 'roles' (visitor, PhD,
SC, member, ...)




Drupal CMS (Content Management System),
http://drupal.org

HiPEAC Review

What We Have Now

•
HiPEAC:

–
Web seminars

–
Announcements

–
Online newsletter

–
Clusters submission &
evaluation

–
Workshops: call for papers +
submission management

–
Private workspace (wiki,
mailinglist, SVN)

–
Jobs (PhD, research, postdow):
seeking/offering

–
Cluster meeting organisation

–
Online journal

–
Taxonomy

–
PhD pages

–
Roadmap

–
Access control based on
membership

HiPEAC Review

•
ACACES

–
Extranet (Program, practical info, ...)

–
Participant management

•
HiPEAC Conference

–
Extranet (Committees, Call for papers,
practical info, ...)

–
Paper submission (Commence)

What We Have Now

HiPEAC Review

HiPEAC Seminars

•
Goal: Offer seminar talks to all network members via video
-
conferencing
equipment, or via recordings available at the HiPEAC website

•
Six seminars have been broadcasted to all HiPEAC members. They were
recorded and are available in the intranet

•
126 downloads from the web.

•
UPC is still the main contributor to this task

–
UPC/INRIA/DELFT tested open tools (eg. VRVS) as a potential infrastructure for
all sites, but discarded it due to technical problems (it was not compatible with
UPC own firewall; video images were really small)

•
Seminars and speakers

–
The Computer Architect: A Unique Opportunity, A Unique Responsibility
,
Yale Patt (University of Texas) (July 12, 2006)

–
Building a Global View for Optimization Purposes,

Ramon Bertran (UPC
-
DAC) (June 8, 2006)

–
Software Aging and Rejuvenation in SOAP
-
based Middleware Tools,

Luis
Silva (Univ. Coimbra) (May 4, 2006)

–
Can Failure Prediction Methods Be Used for Performance Evaluation?

Miroslaw Malek (Institut für Informatik, Humboldt
-
Universitaet zu , Berlin (April
7, 2006)

–
HiPEAC Simulation Workshop

(4 sessions) (February 20
-
24, 2006)

–
Assembly technology for parallel implementation of the large scale
numerical models.

Victor Malyshkin (Russian Academy of Sciences)
(November 23, 2006)

HiPEAC Review

Common Computing Equipment:
Status

•
Sharing middleware (Condor) installed at
FORTH

~64 CPUs for remote use (of 128 CPUs total)

•
Has been installed at INRIA

•
Policy to use

–
Local users full priority

–
Remote jobs run only if NO local job using a system

•
Examined potential for using European
-
level
compute infrastructures

–
Most partners have access to local or remote
resources (mostly compute)

•
Decided to drop this task

HiPEAC Review

The HiPEAC Embedded Systems Roadmap


TU Delft

Sorin Cotofana

TU Delft, The Netherlands

HiPEAC Review

What is a Roadmap?

HiPEAC Review

Why a Roadmap?

•
Linking future to the present

•
Driving Research & Development to the
right path

Present

Demands

Future

Demands

How to get
there?

HiPEAC Review

What are Embedded
Systems?

•
Embedded systems are a combination of
computer hardware and software, and
perhaps additional mechanical or other
parts, designed to perform a dedicated
function.

HiPEAC Review

Embedded Systems Stack

Applications

Fabrication Technology

AMS/RF

MEMS

EDA

Platforms

Digital

Architect.

Market pulls

Technology & Design
methodology push

HiPEAC Review

HiPEAC Embedded Systems


Roadmap Contents

1.
Market Research Projections

2.
Fabrication Technology Advances

3.
Embedded Design Methodologies and Tools

4.
Embedded Processors Roadmap

5.
Embedded Platforms Roadmap

6.
Embedded Application Projections

7.
Case Study: Roadmap for Cell Phone Platforms

HiPEAC Review

Global Embedded Systems

Revenue (by Region)

Source:
“Future of Embedded Systems Technology”
, BCC Co, Inc., 2005

Global Embedded Systems Revenue
0
5
10
15
20
25
30
35
40
Americas
Europe
Japan
Asia-Pacific
Region
$ Billions
0
5
10
15
20
25
AAGR%
2004
2009
AAGR%
AAGR
:

average annual growth rate

HiPEAC Review

Global Embedded Systems

Revenue (by Application)

Source:
“Future of Embedded Systems Technology”
, BCC Co, Inc., 2005

World Embedded Systems Revenue
0
5
10
15
20
25
Telecomm
Consumer
Automotive
Medical/Office
Industrial/Milit.
Application
$ Billions
0
5
10
15
20
25
AAGR%
2004
2009
AAGR%
HiPEAC Review

Global Embedded HW Revenue

Source:
“Future of Embedded Systems Technology”
, BCC Co, Inc., 2005

Global Embedded Hardware Revenue by Category
0
5
10
15
20
25
MPU
MCU
DSP
Memory
ASIC/PLD
Analog
Category
$ Billions
0
5
10
15
20
25
30
AAGR%
2004
2009
AAGR%
MPU

:
microprocessors


MCU:

microcontrollers

HiPEAC Review

Projected Technology Progress

Source:
“
Process
Integration,
Devices and
Structures

”,
ITRS, 2005

Transistor Density MPU (including SRAM)
0
200
400
600
800
1000
2006
2008
2010
2012
Year
Mtransistors/cm2

Transistor number will continue to scale for some time

HiPEAC Review

Embedded Platforms Roadmap

68
14
18
57
19
24
0%
20%
40%
60%
80%
100%
2005
2006
Use of embedded processors in FPGAs
Hard FPGA processor
Soft FPGA processor
No FPGA processor
Source:
“
Survey of System Design Trends
”, Celoxica Inc., August 2005


Hardwired Logic (ASIC
-
like) is being replaced by embedded
processor devices

HiPEAC Review

Embedded Processors: Innovation
driven by Technology + Architecture
Advances

Today
Time
Performance
Architectural
Efficiency
Speed
(Frequency)
33 MHz
100 MHz
200 MHz
450 MHz
1 GHz
3.2 GHz
Pipeline
Superscalar
MMX Technology
Out of Order
Speculative
Hyper
Threading
Source: “
The Era of Tera
”, Pat Gelsinger, Intel, 2005

Multi
-
processing:

Higher throughput

With less speed

HiPEAC Review

Case Study
–


ITRS Mobile Handheld
Roadmap

Year of Production

2006

2009

2012

2015

Process Technology (nm)

90

65

45

32

Supply Voltage (V)

1

0.8

0.6

0.5

Clock Frequency (MHz)

450

600

900

1200

Processing Performance (GOPS)

2

14

77

461

Average Power (W)

0.1

0.1

0.1

0.1

Standby Power (mW)

2

2

2

2

Applications

Real Time
Video Codec

TV Telephone

Source:
“
System Drivers
”, ITRS, 2003


Performance, En. Efficiency (GOPs/W) increase by 200x

HiPEAC Review

ITRS
–

Low
-
Power SoC

Source:
“
System
Drivers
”,
ITRS, 2005

•
Many Processing Elements

•
Reusability, Multi
-
Standard requirements drive for
programmable (processor
-
based) solutions (PEs)


(Heterogeneous) Multi
-
Processor systems
-
on
-
a
-
Chip (SoC)

HiPEAC Review

ITRS
–

Low
-
Power SoC
–

Processing/Performance Trends

Source:
“
System
Drivers
”,
ITRS, 2005

> 100 Processing Elements in 2011 !

HiPEAC Review

Future Embedded System Design Trends

•
Mobile Handset Market driving commercial factor

•
New applications, wireless transmission standards require
high performance embedded computing @ low power

•
ITRS foresees 3x magnitude improvement in performance
and energy efficiency over the next 10 years



(Heterogeneous) Multi
-
Processor system
-
on
-
Chip
Platforms


Compiler Technologies for high
-
performance, low
-
power
embedded computing will be needed


Compiler and System
-
Design Tools for heterogeneous,
massively parallel processing systems and networks

HiPEAC Review



Questions?

HiPEAC Review

WP2
-

Simulation & Compilation
Platforms

HiPEAC Review

Compilation Platform

HiPEAC Review

Two frameworks

•
Last review encouraged early adoption

–
GCC and CoSy strongest candidates

•
D2d Framework Comparative Selection

–
Looked at pros and cons

•
D2g Platform evaluation

–
Community, activities and plans

•
Most interest in GCC

–
Encourage CoSy activity

–
ACE now active members

•
Management

–
A. Cohen lead GCC, B. Franke lead CoSy


HiPEAC Review

CoSy Activities

•
Smaller community than GCC

–
Targeted at irregular processors, typically found in
embedded system

•
ASIP design

–
Custom processors with asymmetric ISA

–
Aachen, ACE, Edinburgh and Imperial

•
Instruction set extension

–
Search for custom instructions

–
Edinburgh Aachen and ACE

•
Design space exploration

–
LisaTek. Edinburgh, Gent, and Aachen

•
Tutorial

–
Rescheduled for HiPEAC ‘07

HiPEAC Review

GCC Activities

•
Tutorials

–
GCC in Grenoble, HiPEAC ‘07, Edinburgh

•
Auto vectorization

–
IBM Haifa, Philips

•
Adaptive optimization

–
INRIA, IBM, ST and Edinburgh

•
A new API for machine learning compilation

•
HiPEAC branch back into mainline

–
30 people contributing

–
11 public meetings, 4 talks

•
Platform engineer (
Cupertino Miranda)

–
Starts in December


HiPEAC Review

Open
-
Source Iterative Compiler


GCC API

Grigori Fursin, INRIA

Collaboration with IBM, Philips (NXP), ST, ARC,

Edinburgh University, Ghent University …

HiPEAC Review

Future compilers with API


Fine
-
grain level optimizations accessible by end
-
user,
prototype is implemented in gcc compiler

API
1


update


IR


decision for

transformation
1

API
2


update


IR


decision for

transformation
2

API
3


update


IR


decision for

transformation
i

Rigid compiler optimization
heuristic “black box”

Program

Optimization

Database

binary

external

compiler

control

perform

transf.
1

perform

transf.
2

perform

transf.
i

compiler transformation toolset

application

HiPEAC Review

Communication with external tools

using transformation xml file (GCC API)

Analysis for
optimization

Decision for
optimization

Analysis for
optimization

Decision for
optimization


application

binary

Decisions and
parameters for
transformations

Compiler
API

Compiler

External output xml file
(program.api.out.xml)

Write mode

Read mode

Decisions and
parameters for
transformations

External input xml file
(program.api.in.xml)

Modified
decisions and
parameters for
transformations

Modified
decisions and
parameters for
transformations

Read/Write
mode

HiPEAC Review

GCC instrumentation to enable API

…


decide_unroll_constant_iterations (loop, flags);


if (loop
-
>lpt_decision.decision == LPT_NONE)


decide_unroll_runtime_iterations (loop, flags);


if (loop
-
>lpt_decision.decision == LPT_NONE)


decide_unroll_stupid (loop, flags);


if (loop
-
>lpt_decision.decision == LPT_NONE)


decide_peel_simple (loop, flags);



/* GCC API2 */


if (flag_api_use)


fapi2_unroll_in(get_name(current_function_decl), loop
-
>num, loop
-
>depth,


&(loop
-
>lpt_decision.decision),




&(loop
-
>lpt_decision.times));



if (flag_api_generate)


fapi2_unroll_out(get_name(current_function_decl), loop
-
>num, loop
-
>depth,




&(loop
-
>lpt_decision.decision),




&(loop
-
>lpt_decision.times));



loop = next;


}


HiPEAC Review

Demo




A tool to demonstrate GCC API:


•
iterative hill
-
climbing search to find best
unrolling factors for a matrix multiply
kernel




HiPEAC Review

Example

Matmul

Small dataset

(3x3 matrices,

27400000 multiplications)

Optimization

Execution time

Speedup

-
O3

5.0 s.

-
O3
–
funroll
-
all
-
loops

(internal factor 7)

3.9 s.

1.3

-
O3
–
funroll
-
all
-
loops

(factor 2 selected with
GCC API)

3.1 s.

1.6

HiPEAC Review

Dissemination of Results

•
Mailing list with 21 subscribers:


https://sympa
-
rocq.inria.fr/wws/info/gcc
-
api

•
Software is publicly available (FSF license):


http://sourceforge.net/projects/gcc
-
api

•
GCC API tutorial (Towards Open
-
Source Iterative
Compiler)


To appear at the 2
nd

HiPEAC GCC Tutorial: “How
To and Return on Experience”


Collocated with the 2
nd

HiPEAC Conference
(Ghent, Belgium, January 29
-
30, 2007)


HiPEAC Review

Demo
-

GCC4CLI

Erven Rohou, ST

HiPEAC Review

Why GCC?

•
Huge effort, freely available

–
over 2 million lines of code

–
15 years of development

–
continuous improvement

•
Widely used

–
robust

–
world wide exposure and acceptance

•
Community

–
get help

–
get testing

HiPEAC Review

How we did it

•
Not a regular GCC backend

–
does not fit GCC machine model

•
Split after GIMPLE passes

–
reuse all existing optimizations

•
SSA
-
based, inlining, autovectorizing, IPA, …

•
For the time being use Portable.NET tools

Approach

HiPEAC Review

Demo Today

ST CLI VM

ST ARM JIT

Nokia 770

ARM 926 TEJ

@ 200MHz

mp3dec.exe

(CLI)

Divisional mp3dec

C code (7KLOC)

GCC4
-
> CLI

HiPEAC Review

Simulation Platform

HiPEAC Review

Simulation Platform
-

Outline

•
Modularity for prototyping, sharing and
comparison

•
Library: current and upcoming simulators

•
Dissemination efforts

•
Online demo of the Shared Memory CMP

•
Transaction
-
Level Modeling for faster and
more simple simulators

•
Simulation speed

•
Full
-
System simulation

•
Simulators services/capabilities

•
Design
-
Space exploration


HiPEAC Review

Modularity for prototyping, sharing and
comparison

Snooper

Snooper

Snooper

PPC

405

PPC

405

PPC

405

Cache

Cache

BUS

Direc
-

-
tory

PPC

405

PPC

405

Cache

Cache

Memory

Memory

Direc
-

-
tory

PPC

405

Cache

Memory

Direc
-

-
tory

PPC

405

Cache

Memory

Direc
-

-
tory

Switch

Memory

Cache

•
Modularity enables
Reuse
,
Sharing

&
Comparison








–
Reuse within simulators (CMP, data & instruction caches)

–
Changing the ISA = Changing the CPU module

–
Sharing eases the Design Space Exploration process

•
Modules can be reused across different simulators


HiPEAC Review

•
Defining a communication interface allows to

–
easily share modules

–
make DSE as simple as swapping modules

Modularity for prototyping, sharing and
comparison

Snooper

Snooper

Snooper

BUS

Memory

const int N = 3;


instance PPC405 cpu[N];

instance Cache cache[N];

instance Snooper snoop[N];

instance Bus bus;


for(int i=0;i<N;i++)

{ cpu[0].out >> cache[0].inCPU;


cache[0].outCPU >> cpu[0].in;



cache[0].outSNP >> snoop[0].inCAC;


snoop[0].outCAC >> cache[0].inSNP;

}


...

class Arm9 : module

{ inport <memreq> in;


outport <memreq> out;


inclock clock;


...

class PPC405 : module

{ inport <memreq> in;


outport <memreq> out;


inclock clock;


...

const int N = 3;


instance PPC405 cpu[N];

instance Cache cache[N];

instance Snooper snoop[N];

instance Bus bus;


for(int i=0;i<N;i++)

{ cpu[0].out >> cache[0].inCPU;


cache[0].outCPU >> cpu[0].in;



cache[0].outSNP >> snoop[0].inCAC;


snoop[0].outCAC >> cache[0].inSNP;

}


...

const int N = 3;


instance
Arm9

cpu[N];

instance Cache cache[N];

instance Snooper snoop[N];

instance Bus bus;


for(int i=0;i<N;i++)

{ cpu[0].out >> cache[0].inCPU;


cache[0].outCPU >> cpu[0].in;



cache[0].outSNP >> snoop[0].inCAC;


snoop[0].outCAC >> cache[0].inSNP;

}


...

const int N = 3;


instance Arm9 cpu[N];

instance
SmartCache

cache[N];

instance Snooper snoop[N];

instance Bus bus;


for(int i=0;i<N;i++)

{ cpu[0].out >> cache[0].inCPU;


cache[0].outCPU >> cpu[0].in;



cache[0].outSNP >> snoop[0].inCAC;


snoop[0].outCAC >> cache[0].inSNP;

}


...

PPC

405

PPC

405

PPC

405

Cache

Cache

Cache

Cache

Cache

Cache

Smarter

Cache

Smarter

Cache

Smarter

Cache

ARM
-
9

ARM
-
9

ARM
-
9

HiPEAC Review

Direc
-

-
tory

PPC

405

PPC

405

Cache

Cache

Memory

Memory

Direc
-

-
tory

PPC

405

Cache

Memory

Direc
-

-
tory

PPC

405

Cache

Memory

Direc
-

-
tory

Switch

Modularity for prototyping, sharing and
comparison

Snooper

Snooper

Snooper

PPC

405

PPC

405

PPC

405

Cache

Cache

Cache

BUS

PPC

405

PPC

405

PPC

405

Cache

Cache

Cache

PPC

405

Cache

Memory

Memory

Memory

Memory

Memory

•
Modularity allow to reuse modules from one simulator to another:









•
From a Shared memory CMP to a Distributed memory CMP

HiPEAC Review

Modularity for prototyping, sharing and
comparison

Direc
-

-
tory

PPC

405

PPC

405

Cache

Cache

Memory

Memory

Direc
-

-
tory

PPC

405

Cache

Memory

Direc
-

-
tory

PPC

405

Cache

Memory

Direc
-

-
tory

Switch

•
From a shared memory CMP simulator, the only new modules for
a distributed memory CMP are:

–
Directory module:

to handle cache coherency in Distribute
environement

–
Switch & Network Interfaces:

To implement more complex
network topologies




Reduced development time

HiPEAC Review

0,98
0,99
1,00
1,01
1,02
1,03
1,04
1,05
1,06
1,07
1,08
1,09
1,10
1,11
VC('82)
TP('82)
SP('90)
Markov('97)
FVC('00)
DBCP('01)
TKVC('02)
TK('02)
CDP('02)
CDPSP('02)
TCP('03)
GHB('04)
Mechanism
Average Speedup
Modularity for prototyping, sharing and
comparison

•
Example of
comparison
: progress in cache research












–
Progress in cache research all but regular (second best mechanism
proposed in 1990)

•
Necessity to compare design options

•
Necessity to have a common infrastructure for facilitating comparison


HiPEAC Review

Library

•
Progressively building a set of interoperable modules/models

Currently in the library:

•
Shared Memory CMP with cache coherency

–
Bus snooping, MESI Protocol

–
PowerPC 405

–
Cache modules (snooping support)

–
DRAM (snooping support)

–
Bus (snooping support)


Next contributions (in coming months):

•
Distributed memory CMP (INRIA)

–
Complex Network topologies

–
Directory based cache coherency

•
PowerPC 405 & 750 with full system support (INRIA/CEA)

•
ARM9 with full system support (CEA / ARM UK)

•
CELL simulator (Barcelona Supercomputing Center)

•
ST231 VLIW instruction set & cycle level simulator (INRIA)


Later contributions:

•
PowerPC 970 (CEA / INRIA)

•
Generic out of order superscalar processor (OoOSysC)

HiPEAC Review

Library
-

Module Repository

modules

memreq.h

common.h

mem_common.h

base

error.h

utility.h

bus

debug

markup

system

bus.sim

stop_at_cycle.sim

ten.sim

CacheContainer.h

MemoryContainer.h

cpu

memory

powepc405

cache

dram

simple_memory

powerpc405

CachePPC.h

common_ppc.h

i.h

Pipeline.h

ppc_instruction.h

CpuPPC405.sim

cache

CacheComon.h

CacheWB.sim

dram

dram_components.h

dram.sim

simple_memory

types.h

simple_memory.sim

HiPEAC Review

3 750
21 818