ENGR-43_Lec-12c_FETs ... - Chabot College

amountdollElectronics - Devices

Nov 2, 2013 (3 years and 7 months ago)

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BMayer@ChabotCollege.edu
• ENGR
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

1

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Bruce Mayer, PE

Registered Electrical & Mechanical Engineer

BMayer@ChabotCollege.edu

Engineering 43

FETs
-
3

(Field Effect Transistors)

BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

2

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Learning Goals


Understand the Basic Physics of
MOSFET Operation


Describe the Regions of Operation of a
MOSFET


Use the Graphical LOAD
-
LINE method
to analyze the operation of basic
MOSFET Amplifiers


Determine the Bias
-
Point (Q
-
Point) for
MOSFET circuits

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

3

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Learning Goals


Analyze the I/O relationship for

small
-
signal Amplifiers


Determine the
OutPut

for Various
CMOS Logic Gates

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

4

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

“Common”


What does it mean?


“Common” is an electronics term that
usually means a
digital
-
GROUND of
Some Sort.


Recall that in the small Signal Case that
VDC Sources
are effectively SHORTS
to the Small
-
Signal “Common”, or GND
Connection


Example: A “common
-
source” MOSFET
amp has the source connected to small
-
signal GND somehow

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

5

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Refined Small Signal Model


The KCL Equation for the model

that accounts for the

upward
i
D

Slope in SAT


The Graphical Representation

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

6

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Common Source Amplifier


A typical “CS” Amp Circuit

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

7

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Common Source Amplifier


Analyze,
Qualitatively the CS
Amp Circuit







Recall for Caps


SHORTS to fast AC


OPENS to DC


C
1

and C
2

are
“Coupling”
capacitors



C
1

couples the input
to the MOSFET gate


C
2

couple the Output
to the Load, R
L


C
S

connects the
FET Source
-
Connection to GND
(or Common)

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

8

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Common Source Amplifier


Analyze,
Qualitatively the CS
Amp Circuit







Resistors R
1
, R
2
, R
D
,
and R
S

form the
Bias
Network


The Bias Network is
designed to set the
Q
-
Point to allow a
large swing
in the
output signal,
v
o
, as
a result of large input
Voltage
(
v
in

=
v
gs
)
Changes.


The FET MUST
Remain in
SATURATION during
the entire Swing

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

9

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CS
-
Amp Small Signal Model


Recall the Small Signal FET Model from
Last time


Note that
Caps

&
DC
-
Srcs

are
Shorts


Yields the small signal Model

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

10

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Large

S浡ll

Signal Model

→ Short

To AC

Signals

𝐺

𝑆

𝐷

𝐺𝑁𝐷

𝐺𝑁𝐷

BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

11

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CS
-
Amp Voltage Gain


By Parallel Resistors


Use these
equivalent
Resistances to
simplify the small
signal
Ckt


Also define
v
in

and
v
o

for the equivalent
circuit

BMayer@ChabotCollege.edu
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

12

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CS
-
Amp Voltage Gain


By V
-
Divider on Left
Loop



On Right (
OutPut
)
Loop


Thus by Ohm



Also


Thus A
v
:

BMayer@ChabotCollege.edu
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

13

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CS
-
Amp input Resistance


Recall R =
∆V/∆I


For the Common
Source Amp



From

Before


Thus
R
in

BMayer@ChabotCollege.edu
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

14

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CS Amp
OutPut

Resistance


To find the
OUTput

Resistance


Set v(t) = 0


i.e.; it becomes a
SHORT


Disconnect Load R
L


Find R Looking into
the R
L

terminals


This Produces the
R
o

circuit


Since
v
gs

= 0 V, then
g
m
v
gs

= 0 amps


i.e.; the dependent
current source is OPEN


Thus can Find R
o

by
Parallel combination

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

15

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Check by
Thévenin
:
𝑹
𝒐
=
𝒗
𝒐𝒄
𝒊
𝒔𝒄


BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

16

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Check by
Thévenin
:
𝑹
𝒐
=
𝒗
𝒐𝒄
𝒊
𝒔𝒄


BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

17

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

18

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


Notes on SF
Ckt


R is the internal

(
Thévenin
)

resistance of the

input source


C
1

and C
2

are Coupling Capacitors


They are SHORTS to the Small Signal


R
1
, R
2
, and R
S

form the Bias (Q
-
Pt)
Network


In Small
-
Signal
v
d

connected to GND

BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

19

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

SF Large Signal Model

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

20

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

SF Large Signal Model

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

21

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


Note that in this case the DRAIN is
connected to DC
-
Source V
DD
; a SHORT
to the Small Signal.


Then the Small Signal Model

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

22

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

SF Small Signal Model

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

23

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


Again, Equivalent
Resistances






Note that in this
Circuit the Drain is
at the Bottom
(
GND’d
), and
Source is at the Top


Then the Equivalent
Model





By Ohm on the
Rt


BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

24

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


Note that the


Source is at the
v
o

Voltage


Gate is at the v
in

Voltage
as
i
in

=0


Then by KVL on

a clever Loop

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

25

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


But

recall


Substitute out
v
o

in
the previous
Eqn




Then the Voltage
Gain (amplification)


Factor out
v
gs




Cancelling
v
gs

Find
in the Small Signal
Case:

BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

26

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


The Input
Resistance





For R
o



Set v(t) = 0


i.e.; Short it


Remove R
L


Apply a Voltage
PROBE to SD
Connections


The probed Circuit





Then R
o

=
v
x
/i
x



Note that v
in

= 0 (no
Pwr

Src
) → G
-
terminal is at GND

BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

27

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Source Follower Circuit


And
v
s

fixed at
v
x

so




Now KCL at Top
-
Right node (in = out)




Subbing out
v
gs


Collecting Terms






Then R
o

=
v
x
/i
x


BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

28

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Recall from Chp7 Logic Gates


Truth Tables Describe the I/O behavior
of Logic Gates, but NOT how they are
constructed


Most Modern Logic gates are built

from collections of MOSFETS

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

29

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Alternative Symbols for MOSFETs


n
MOSFETs


“ON”: when V
GS

POSITIVE



p
MOSFETs


“ON”: when V
GS

NEGATIVE

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

30

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Alternative Symbol Meaning


The Arrow shows the direction of
Current flow in SOURCE Connection






In an
n
FET

current flows:
Drain→Source


Current flows OUT of the source when FET On


In a
p
FET

current flows:
Source→Drain


Current flows Into the Source when FET On

nFET

pFET

BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

31

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS


What is it?


“CMOS” it the technology used in
Digital Integrated Circuits such as
MicroProcessors
. The Meaning


C ≡ Complementary ← The key


M ≡ Metal


O ≡ Oxide


S ≡ Silicon

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

32

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Complementary Logic


In Perfect Complementary Logic circuits
every
nFET

(or
pFET
) has it’s opposite,
or complementary
pFET

(or
nFET
)


Example:

CMOS

Inverter

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

33

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Switch Model for CMOS Logic
Ckts


The INPUT to CMOS Logic Circuits is
assumed to be DIGITAL; that is the
Input is one of


Hi

(usually V
DD
)
OR

Lo

(usually GND)


Example: CMOS Inverter

(a)
Input is

Lo
;

Output
is
Hi

(a)
Input is

Hi
:

Output
is
Lo

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

34

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS Inverter Summarized


Note that SOURCE and
BODY are “tied Together”


This is very typical for
Enhancement Mode MOSFETS


A third Alternative seen in
Logic
Ckt

Analysis is the
“Invert BUBBLE” on the
pFET

nFET

pFET

BMayer@ChabotCollege.edu
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43_Lec
-
12c_FETs
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3_MOSamps_MOSgates.pptx

35

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Invert
-
Bubble Inverter Circuit


Using the
Inversion
-
Bubble
facilitates drawing
and analysis of
CMOS Logic
Circuits.


The “Bubble”
Version of the
Inverter
ckt

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
-
3_MOSamps_MOSgates.pptx

36

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS Voltage Levels for 1 & 0


As discussed previously a “digital” 1 or
0 is represented by a RANGE (analog)
of Voltage Levels. For typical CMOS

BMayer@ChabotCollege.edu
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

37

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS NAND Gate


NAND:
All

Hi → Lo,
else

Hi

Basic Circuit

A
-
Hi &
B
-
Lo

V
out

Connected
to
V
DD

BOTH
A

&
B

Hi

V
out

Connected
to GND









BMayer@ChabotCollege.edu
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

38

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS NAND “Switch” Analysis


Drawing the FETs as switches can
Speed and/or Clarify the output analysis









BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

39

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS NAND “Bubble” Analysis

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

40

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS NOR Gate


NOR:
Any

Hi → Lo,
else

Hi

Basic Circuit

A
-
Hi &
B
-
Lo

V
out

Connected
to GND

BOTH
A

&
B

Lo

V
out

Connected
to
V
DD









BMayer@ChabotCollege.edu
• ENGR
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43_Lec
-
12c_FETs
-
3_MOSamps_MOSgates.pptx

41

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS NOR Switch Analysis


NOR:
Any

Hi → Lo,
else

Hi

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

42

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

WhiteBoard

Work


Determine the TRUTH Table for the
CMOS Logic Gate Below

BMayer@ChabotCollege.edu
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12c_FETs
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3_MOSamps_MOSgates.pptx

43

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

All Done for Today

Typical

CMOS gate

I/O Curve


CMOS Inverter

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

44

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Bruce Mayer, PE

Registered Electrical & Mechanical Engineer

BMayer@ChabotCollege.edu

Engineering 43

Appendix

Other CMOS Gates


BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

45

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

BMayer@ChabotCollege.edu
• ENGR
-
43_Lec
-
12c_FETs
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3_MOSamps_MOSgates.pptx

46

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

DC
Srcs



SHORTS in S浡ll
-
Signal



In the small
-
signal equivalent circuit DC
voltage
-
sources are represented by
SHORT CIRUITS; since their voltage is
CONSTANT, the exhibit ZERO
INCREMENTAL, or SIGNAL, voltage


Alternative Statement: Since a DC
Voltage source has an ac component of
current, but NO ac VOLTAGE, the DC
Voltage Source is equivalent to a
SHORT circuit for ac signals

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

47

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

Ways to Make 1’s & 0’s

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12c_FETs
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3_MOSamps_MOSgates.pptx

48

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

3
-
Input NAND

Ref: 2010
-
005.
Wakerly

-

Chapter_03
-

logic gates_VERYGood.pptx

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

49

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

CMOS Buffer (Unity Gain)


Inverters in SERIES

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12c_FETs
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3_MOSamps_MOSgates.pptx

50

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

AND Gate

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3_MOSamps_MOSgates.pptx

51

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

AND
-
OR
-
INVERT gate

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12c_FETs
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3_MOSamps_MOSgates.pptx

52

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

AND
-
OR
-
INVERT gate SYMBOL

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12c_FETs
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3_MOSamps_MOSgates.pptx

53

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

OR
-
AND
-
INVERT gate

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12c_FETs
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3_MOSamps_MOSgates.pptx

54

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

OR
-
AND
-
INVERT gate SYMBOL

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

55

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

HC CMOS Logic
-
Family Noise
Lvls


Noise levels

BMayer@ChabotCollege.edu
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12c_FETs
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3_MOSamps_MOSgates.pptx

56

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis

BMayer@ChabotCollege.edu
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43_Lec
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12c_FETs
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3_MOSamps_MOSgates.pptx

57

Bruce Mayer, PE

Engineering
-
43: Engineering Circuit Analysis