Design of a 4- bit Shift Register

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Nov 2, 2013 (4 years and 9 days ago)

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ChipWise Tutor Workbook


02/11/13




1


NAME


LOGIN


COURSE


1) Aims

The aim of ChipWise Tutor is to expose you to the design and simulation of CMOS VLSI circuits at
both circuit and logic level. This is achieved through exercises, which cover circuit level design and its
effect on perform
ance, stick layout, simulation at transistor level and switch level and hierarchical
design. The subject is presented in seven parts:




A Tutorial Guide to ChipWise



Transistor Sizing of a Logic Inverter



Design and Simulation of Simple Logic Gates



Design
of a 4
-
bit Shift Register



Design of a Parallel Load Shift Register



Design of a Universal Logic Module using a 4:1 Multiplexer



Design of a Parity Generator

2) The Workbook

This workbook is for you to log results as you work through the ChipWise Tutor cou
rse material. For each
frame in this workbook, there is a corresponding workbook icon in the Web based courseware. As you
work through ChipWise Tutor, whenever you see a workbook icon, you know you must complete the
appropriate frame in the workbook. It sh
ould be handed in to your demonstrator when you have finished.

3) Screendumps

Throughout this workbook, you will be asked to paste in the appropriate screendump from
ChipWise. To do this, follow these steps:




Select the
Monochrome

option from the required
window's men
-
bar.



Press
<Alt
-
Print Scrn>
to copy the current window into the clipboard buffer.



Place the cursor in the appropriate frame in the workbook, and use the
Paste

command from the
MS Word
Edit

menu to copy the screendump into the workbook.



Select
the pasted image and scale it to fit the frame.

4) Module 1: A Tutorial Guide to ChipWise

For the first module
, A Tutorial Guide to ChipWise
, there is no need to take notes … just work through
the tutorial to get a feel for using the ChipWise design system

and the Web based courseware which guides
you in using the tools.

Week
15,

2000
/01


ChipWise Tutor Workbook


02/11/13




2

Module 2: Transistor Sizing of a Logic Inverter

2.2 DC Analysis of Logic Inverter


P
-
type width = N
-
type width

Vinv = ………………………………………….


P
-
type width = 2.5 x N
-
type width

Vinv = …………………
……………………….


Why is this value closer to Vdd/2 than before?






2.3 Transient Analysis of a Logic Inverter

P
-
type width = 2.5 x N
-
type width


Rise Time = ………………………………

Fall Time = …………………………
……


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3

P
-
type width = N
-
type width



Rise Time = ………………………………
=
Fall Time = ………………………………




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4

Module 3: Design and Simulation of Simple Logic Gates

3.4 Device Sizing and Simulation of the NAND gat
e


Minimum Sized Transistors


Waveforms A

Rise Time = ………………………………

Fall Time = ……………………………….


The 2
-
input NAND gate



Minimum Sized Transistors


Waveforms B

Rise Time = ………………………………

Fall Time = ……………………………….


Explain the above results








Width
of N
-
type transistors doubled


Rise Time = ………………………………

Fall Time = ………………………………


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5

3.5 Design and Simulation of a 2
-
Input NOR Gate

Minimum Sized Devices


Rise Time = ………………………………

Fall Time = ………………………………


Sketch the circuit diagram of the 2
-
input NOR gate in
this frame













Explain Your Results






What should the widths of the devices be if we wish to have rise and fall
times at least as fast as the
sized logic inverter? Explain Your Results.

Size of N
-
type devices (in microns) ………… Size of P
-
type devices (in microns) …………



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6

Module 4: Design of a 4
-

bit Shift Register

4.2 Circuit Level Simulation of sreg


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reendump from the output of SVIEW into this frame


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7

4.6 Logic Level Simulation of sreg



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8

Module 5: Design of a Parallel Load Shift Register

5.1 Derivation of Circuit Diagram from a Stick Diagra
m

Transistor
-
level circuit diagram

Circuit Level Simulation of Shift Register Cell



Sketch the transistor
-

level diagram of the shift register circuit in this frame



Paste the screendump from the output of SVIEW into this frame



Sketch the logic level d
iagram of the shift register circuit in this frame


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9


5.2 Design of one
-
bit Shift Register Cell with Parallel Load

Symbolic Level Design of Modified Shift Register Cell




Explain how the shift register cell operates



Paste the screendump of the modified s
hift register cell into this frame


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10

Circuit Simulation of modified Shift Register Cell


Circuit Diagram of Modified Shift Register Cell


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Sketch the circuit diagram of the modified shift regis
ter circuit in this frame


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11



5.3 Design of a 4
-
bit Shift Register with Parallel Load

Logic Level Simulation of
preg4



Serial Input Mode





Describe briefly the operation of your modified cell with reference to the simulation results



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rom the output of SVIEW into this frame


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12

Logic Level Simulation of
preg4



Parallel Load Mode


Mask Level Design of preg4


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Paste the screendump of preg4 into this frame


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13

Logic Level Simula
tion of
preg4

with given waveforms



The following waveforms will cause the register to parallel load ‘0101’ and then to serially shift it out of
q3 whilst loading new data through d0:




Paste the screendump from the output of SVIEW for the above input wa
veforms, into this frame


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14

Module 6: Design of a 4:1 Multiplexer

6.1 Design of a 4:1 Multiplexer


Circuit Level Simulation of 4:1 Multiplexer cell



Maximum voltage swing = ………………………………………….

Minimum voltage swing = …………………………………………..



Explain the effect











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15


Improving the Output Swing

This circuit, added to the output of the Multiplexer,
improves the output swing of your Multiplexer





Explain how transistor Tp and the inverter
impr
ove the output voltage swing of the circuit






An interesting experiment that you can carry out is to monitor the current drawn by the inverter when
‘out’ is high and compare that to the current drawn under the same circumstances but with Tp removed.
Ex
plain the difference.






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16


6.2 Use of a 4 to 1 Multiplexer as a programmable Logic Element



Paste the screendump of your stick diagram into this frame


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17



The circuit on the left can be used to generate
various logic functions of a and b under the contro
l
of [c3 … c0]. From the result of the circuit level
simulation of this circuit with 0V applied to c3, 5V
applied to c2, c1 and c0, identify the logic function
produced.







Identify the logic levels which need to be
applied to [c3 … c0] to achieve the

logic
functions shown.


function

c3

c2

c1

c0

1

a + b





2

a EXOR b





3

a AND b





4

b





5

1









Sketch the floorplan of a structure , based on the programmable Logic Element, which can be used in
an ALU to produce various logic funct
ions of two 16
-
bit words, showing the flow of Data and Control.


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18

Module 7: Parity Generator Cell

7.2 A VLSI Implementation of a Parity Generator Cell


The circuit shown below

can be used as a Parity
Generator Cell:





Circuit Level Simulation of the Parity Cell


Paste the screendump of your stick diagram of the Parity Cell
into this frame



Paste the screendump from the output of SVIEW for the circuit level simulation of the Parity Cell, into this frame


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19

Circuit Level Simulation of Parity Cell with lev
el
-
restore stage




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20

7.3 An 8
-
bit Parity Generator


Circuit Level Simulation of an 8
-
bit Parity Generator



The circuit level simu
lation of the one
-
bit parity cell showed an output logic 1 voltage of approximately
4Volts. What is the output voltage swing of the 8
-
bit parity generator?




Explain the result






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21

Logic Level Simulation of an 8
-
bit Parity Generator



Comment on any differences between these results and those obtained from circuit level simulation with
SPICE.







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mp from the output of SVIEW into this frame