DESIGN AND ANALYSIS OF 1KB 6T SRAM CELL IN DEEP SUBMICRON CMOS TECHNOLOGIES

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DESIGN AND ANALYSIS OF 1KB 6T SRAM CELL IN DEEP
SUBMICRON CMOS TECHNOLOGIES


1

MR P.J.DALVADI
,

2

MR. R

.J.ACHARYA
,

3
PROF.

K.M.PATTANI


1

M
.
E
.[
Electronics & communication
]
Student
,
Department
Of
E&C,

C.U.Shah

College
o
f
Engineeri
ng
a
nd
Technology
,
Wadhawan
,
Gujrat

2
M.E.[Electronics & communication] Student, Department Of E&C,
C.U.Shah

College o
f
Engineering
a
nd Technology, Wadhawan,Gujrat

3
Asst
.

Professor
,
Department
Of
E
&
C Engineering
,

C.U.Shah

College of Engineering a
nd
Technology, Wadhawan,Gujrat


pra
vindalvadi@yahoo.c
om
,
rahulacharya.ec@gmail.com,
kunalpattani@gmail.com

ABSTRACT
:




VLSI industry is mainly concentration mini mum

power consumption

and less area
.

The goal of
this paper is to reduce power and area of Static Random Access Memory (SRAM)
.
He
re 1kb

six
-
transistor (6T)
SRAM cell is

designed using deep submi cron (65nm, 45nm)

CMOS technologies. Then
i t is simulated using
LTSPICE for

check
ing

its functionality, Total
power dissipation
, read access time and wri te access time.

Compared to 6T SRAM ce
ll of
both
d
eep submicron CMOS technologies,

45nm CMOS t
echnology has
45%
less
power consumption
an
d less area required due to reduced
channel

l ength of CMOS transi stor

compared to
65nm CMOS technology.






Keyw
ords
--
6T SRAM cell, less power, read access

time, write access time, 1kb, CMOS technologies

I.

I
NTRODUCTION

In today technol ogical changes happeni ng, there i s a
huge demand for fi ndi ng out devi ces wi th l ow power.
The demand of l ow power becomes the key of the
VLSI desi gns rather than hi gh speed, p
arti cularl y i n
embedded SRAMs and caches

[
3
]
.

In deep submi cron
CMOS technol ogy, we scal ed down channel l ength of
CMOS transistor, so that area of CMOS transistor is
l ess. If area reduced then automati call y power i s l ess
consumpti on.
A few cri ti cal ci rcui t
s i n a system not
onl y affect the desi gn metri cs but may fail to operate
i n deep submi cron technol ogy. Hence the SRAM
arrays are desi gned, anal ysed and checked for i ts
desi gn metri cs i n deep submi cron CMOS
technol ogi es
.

S
i x
-
transistor (6T) SRAM cel l i s
sho
wn i n Fi g

1. 6T
SRAM cel l consists of two cross
-
coupl ed i nverters
(M1
-
M3 and M2
-
M4)

[
1
-
3
]
.




Fi g

1
.
S
i x
-
transi stor (6T)
SRAM
cel l

Transistors connected to the bi tli nes are call ed
access transistors
(M5
-
M6). T
ransistors pull the cell

val ues

to
V
DD

are cal
l ed l oad transistor (M3
-
M4), and the
ones connected to ground are call ed dri ver
transi stors (M1
-
M2)
.

Thi s paper revi ew secti on wi se as under as: Secti on II
deals wi th 1kb SRAM structure
,
secti on III deals wi th
Wri te/Read Operati on of both SRAM cel l
, si mula
ti on
and resul ts are di scussed i n secti on IV. Fi nall y the
concl usi on i s gi ven i n secti on V.

II.

1KB 6T SRAM CELL STRUCTURE


Fi g

2
Shows 1kb 6T SRAM cel l structure
.



Fi g 2.
1kb 6T SRAM
cel l S
tructure

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1kb SRAM structure has 32 rows and 32 col umns of
SRAM cel l.
Row i ndicates wordli ne of SRAM cel l.
Col umn i ndi cates bi tli ne of SRAM cel l

[
4,
6
-
7]
. In
fi gure has some other circui t li ke wri te dri ver

circui t
,
precharger ci rcui t, address decoder and sense
ampli fi er, whi ch has special functi on for the SRAM
cel l.

A: WRITE
DRIVER CIRCUIT

The functi on of the SRAM wri te dri ver i s to wri te
i nput data to the bi tl i nes when Wri te Enabl e (WE)
si gnal is enabl ed; otherwi se the data is not wri tten
onto the bi tli nes

[1]
. Onl y one wri te dri ver i s needed
for each SRAM col umn. The schemat
i c of the wri te
dri ver c
i rcui t i s shown i n Fi g 3
.





Fi g
3
.
Wri te Dri ver Ci rcui t

B
: PRECHARGE CIRCUIT

The functi on of the precharge ci rcui t i n the 6T SRAM
array is to charge the Bi t Li ne (BL) and Bi t Li ne Bar
(BLB) to V
DD

[6
, 14
]
.

The schemati c of the p
recharge
ci rcui t for the 6T SRAM array i s shown i n

Fi g

4
.

The transi stor M1 and M2 will precharge the
bi tli nes whi l e the transistor M3 wi ll equali ze them to
ensure both bi t l i nes wi thi n a pai r are at the same

Potenti al

before the cel l i s read.




Fi g
4
.

P
recharge Ci rcui t


C: ADDRESS DECODER

Address decoder is used to decode the gi ven i nput
address and to enabl e a parti cular wordli ne (WL). In
particul ar dynamic NAND

CMOS
decoder i s used

[
9
-
12]
. For an n
-
word memory, an
m: n
dynamic NAND
CMOS
decoder i s use
d where m=l og2
n
. The
schemati c of 2:4 dynami c NAND
CMOS
decoder i s
shown i n Fi g 5
. 5:32 dynami c NAND CMOS
decoder
made for 1Kb SRAM cel l.
Accordi ng to sel ecti on of
i nput we can enabl e parti cul ar wordli ne row of
SRAM structure.
Al l the outputs of the array
are

hi gh
by defaul t, wi th the excepti on of the sel ected row,
whi ch is l ow. Si nce the i nterface between decoder
and memory

often i ncl udes a buffer, i t can be made
i nverti ng to enabl e the WL
.




Fi g .5

2:4 Dynami c NAND Decoder

D:
SENSE AMPLIFIER

The functi o
n of SRAM cel l i n Sense ampli fi ers (SA) is
sensi ng si gnal from BLB and BL. Sense ampl i fi e
r is an
i mportant component i n m
emory desi gn. One of the
major issues i n the desi gn of SRAMs

i s the speed of
read operati on
. SA i s presen
t i n every col umn of
SRAM arra
y

[1,

6
, 11
]
.
Fi g. 6

shows
SA
circui t for the
6T SRAM array.
Usi ng the approxi mate val ues, the
si mulati ons were run and the wi dths were opti mi zed
to get the best output. The read operati on begi ns by
prechargi ng and equali zi ng both the bi tli nes, wi th
si mul t
aneousl y bi asi ng the l atch
-
type SA

[12]

i n the
hi gh
-
gai n meta
-
stabl e regi on by precha
rgi ng and
equali zi ng i ts i nputs
.
And then to read a parti cular
word from the SRAM array, the correspondi ng row is
sel ected by enabl i ng the WL. Once a suffi ci ent
vol tage di
fference is buil t between the bi tli nes, the
SA i s enabl ed by read enabl e (RE) si gnal. The SA wi ll
sense whi ch bi tli ne is headi ng towards hi gh vol tage
and whi ch bi tli ne is headi ng towards ground
potenti al and then a ful l vol tage swi ng i s obtai ned at
the out
put.



Fi g

6.

l atch
-
type SA for 6T SRAM cel l

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III.

Write/Read Operation

Fi rstl y the wri te operati on of the cel l i s descri bed as
foll ows.
Wri te operati on means store data i nto the
nod of SRAM cel l.

In order to store l ogi c “1” to the
cell, BL is charged to V
DD

an
d BLB

is charged to
ground and vise verse for stori ng l ogic “0”. Then the
wordli ne vol tage is swi tched to V
DD

to turn “on” the
NMOS access transi stors. When the access
transistors are turned on, the val ues of the bi
tli nes
are wri tten i nto Q and QB

[2]
.

Th
e read operati on
means data read from the SRAM
cell.

To read from the cel l the bi
tl i nes are charged to
ground i nstead

of V
DD

and the wordl i ne vol tage is set
to V
DD

to turn on the NMOS access transi stors. The
node wi th l ogi c “1” stored wi ll pull the vol tage

on
the correspondi ng bi tl i ne up to a hi gh (not Vdd
because of the vol tage drop across the NMOS access
transistor) vol tage l evel. The other bi tli ne is pull ed to
ground. The sense ampl i fi er will detect whi ch bi tli ne
is at a hi gh vol tage and whi ch bi tli ne is

at ground

[6]
.
If the cel l was stori ng
l ogi c “0” the vol tage l e
vel of BL
wi ll be l ower than BLB

so the sense ampli fi er will
output l ogi c “0”. If the cel l was stori ng l ogic “1” then
the vol tage l ev
el of BL wi ll be hi gher than BLB
then
the sense ampl i fi er w
i l
l output
l ogi c “1

.

IV.

SIMULATION

AND

RESULTS

The fol l owi ng confi gurati on of SRAM arrays were
desi gned and anal ysed usi ng the Standard 6T SRAM
Cel l: (a) 1*1

(1 bi t) (b)

16
*16 (256 bi t) (c) 32*32 (1
kb)
.

Vari ous confi gurati on of SRAM structure were
si mulated

usi ng
LTSPICE

software

i n (65nm, 45nm)
CMOS technol ogi es.

The
functi onali ty

Wri te/read
operati on

of 1*1

(1 bi t)

6T SRAM cel l

i n

65nm, 45n
are

shown i n Fi g 7

and
Fi g 8
.


The functi onal i ty
Wri te/read operati on

of 16*16 (256 bi t) 6T SRAM
cell i n 65nm, 45nm a
re shown i n Fi g

9 and

Fi g
10
.
The functi onali ty
Wri te/read operati on

of 32*32
(1kb
) 6T SRAM cel l i n 65nm, 45nm are shown i n Fi g
11 and

Fi g
12
.
Show

all the fi gures
functi onali ty of
the SRAM cel l
wri te 1


read 1


wri te 0


read
-
0.

Foll owi ng are the si gnals

used i n the si mulati on
resul ts: ‘pc’ corresponds to PC si gnal gi ven to the
Precharge Circui ts; ‘wl ’ corresponds to the WL si gnal
of row i n the SRAM array. Thi s i s the output of
i nverti ng buffer ci rcui t; ‘we’ corresponds to the wri te
enabl e si gnal gi ven to

the wri te dri ver ci rcui ts; ‘di ’
correspond to i nput data bi ts; ‘l pc’ corresponds to
the Precharge si gnal gi ven t
o the Local Precharge
circui ts;
‘re’ corresponds to the read enabl e si gnal
gi ven to the sense ampli fi er circui ts; ‘q’ correspond
to storage no
de Q, ‘q1’ correspond to storage node
QB of the SRAM. For the 256bi t has fi rst row
sel ected i n getti ng out resul t of col umn 0 and 15.

For
the 1kb has fi rst row sel ec
ted and getti ng out of
col umn 0,

col umn 15 and col umn 31.
Accori ng to
CMOS parameter fi l e
V
DD
=1.1V (i n 65nm CMOS
technol ogy) and V
DD
=0.9V (i n 4
5nm CMOS
technol ogy).


Fi g 7. 1*1
Wri te /read operati on of 6T SRAM cel l i n
65nm CMOS technol ogy


Fi g 8. 1*1
Wri te /read operati on of 6T SRAM cel l i n
45nm CMOS technol ogy




Fi g 9.
16*16

Wri te
/read operat
i on of 6T SRAM cel l i n
65nm CMOS technol ogy

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Fi g 10. 16*16
Wri te/read operati on of 6T SRAM cel l
i n 45nm CMOS technol ogy


Fi g 11.
32*32
W
ri te
/read operati on of 6T SRAM cel l
i n 65nm CMOS technol ogy



Fi g 12. 32*32
Wri te/read operati on of 6T SRAM cel l
i n 4
5 nm CMOS technol ogy

Access ti me i s most i mportant parameter for SRAM
operati on. Access ti me i s nothi ng but propagati on
del ay to getti ng proper SRAM operati on
.

The Read
Access ti me i s the ti me measured from the poi nt at
whi ch the RE si gnal reaches 10% of V
DD to the poi nt
at whi ch the output si gnal becomes +/
-

10% VDD of
the requi red l ogi c val ue

Sense ampl i fi er required
some ti me to sensi ng output from ‘BLB’ and ‘BL’.
The Wri te Access ti me is the ti me measured from
the poi nt at whi ch the WE reaches 50% of
VDD to
the poi nt at whi ch the storage node of the cel l
reaches 50% of VDD. SRAM requi red some ti me to
stored val ue at node QB and Q. Read access ti mes
and wri te access ti me for
6T
SRAM cel ls resul t show
i n tabl e .1

1KB SRAM cel l

65nm

CMOS

Technol ogy

45n
m

CMOS

Tech
-
nol ogy

Read Access Ti me

304 ps


232.52 ps

Wri te Access Ti me

97.93 ps

87
.42 ps

Tabl e
1
.

Read Access Ti me and Wri te Access Ti me of
1 kb 6T SRAM cel l


Power di ssi pati on is mai nl y consi derabl e parameter
whi l e desi gni n
g any memory. Here we
have used
65nm and

45nm CMOS Technol ogy.

Power = I
D
avg * V
DD


power di ssi pati on of
di fferent confi gure 6T
SRAM
cell s

i n
65nm

CMOS technol ogy resul t show i n tabl e
2, 4
5nm

CMOS technol ogy
resul t shown i n tabl e 3.

CMOS T
echnol ogy

Confi guration

TDP



65
nm

1*1

37.4946 µw

16*16

696.4672 µw

32*32

1412.22
µw

Tabl
e

2. Power D
issipation of 6T SRAM Cell In 65
nm
CMOS Technology.

CMOS
Technology

Configuration

TDP



45nm

1*1

20.73 µw

16*16

383.44 µw

32*32

768.00 µw

Table
3. Power
Dissipation of 6T
SRAM Cell In 4
5nm
CMOS Technology

The total number of transistors used for various
configurations of
6T
SRAM cells has be
en tabulated
as shown in Table 4
.

If we reduce the CMOS
technology then we have scale down channel len
gth
of transistor. so that automa
tic reduce the area of
CMOS transistor structure. So that 45nm CMOS
technology has required less ar
ea compared to other
technology
.


Configuration

Total number of transistor
s

1*1

31T

16*16

2136 T


32*32

7402 T


Tabl e

4
. Total Number of Transi stors


V.

C
ONCLUSION

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1 kb 6T
SRAM cel l is desi gned i n

65nm, 45nm CMOS
technol ogi es.

Above al l the resul t from we can
concl ude that
small er

deep submi cron

CMOS
technol ogy is

used

l ess power consumpti on and l ess
area requi red. Here 45nm CMOS technol ogy has
45%
l ess pow
er

consumpti on compared to 65 CMOS
technol ogy and al so l ess area
.



VI.
REFERENCES

[1]Sandeep R , Narayan T Deshp
ande , and A R
Aswatha, “Desi gna
nd Anal ysis of a New Loadl ess 4T
SRAM Cel l i n Deep Submi cron CMOS Technol ogi es”,
Second Internati onal
Conference on Emergi ng
Trends i n Engi neeri ng and Technol ogy, ICETET
-
09..

[2]
Ji nshen Yang and Li Chen, “A New l oadl ess 4
-
transistor SRAM cel l wi th a 0.18μm CMOS
technol ogy”, El ectri cal and Computer Engi neeri ng,
CCECE Canadian Conference, pp. 538


541, Apri l
2007.

[3
]

Sreerama Reddy G.MP, Chandrashekara Reddy,
‘‘
Negati ve Word
Li ne Scheme Based Low Power 8Kb
SRAM for Stand Al one Devi ces
”, European Journal of
Sci enti fi c Research

[4]James S. Caravella, “A Low Vol tage SRAM for
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-
State
Ci rcui ts, vol. 32, no. 3, pp. 428


432, March 1997

[5]

Yen
-
Jen Chang, Shanq
-
Jang Ruan, and Fei pei Lai,
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-
Power Cache usi ng Two
-
Level Fi l ter Scheme”, IEEE Transacti ons on Very
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pp.568
-
580, August 2003

[6]Andrei Pavl ov and Mano
j Sachdev, “CMOS SRAM
Ci rcui t Desi gn and Parametri c Test i n Nano
-
Scal ed
Technol ogi es”, Spri nger, 2008 .

[7]R. Jacob Baker, CMOS Circui t Desi gn, Layout and
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[8]
Nestoras Tzartzanis, “Hi gh Performance Energy
-
Effi ci ent Desi gn”, p 89
-
119, Spri nger 2006.

[9]Jan.M.Rabaey, Anantha.P.Chandrakasan, and
Bori voje Ni kolic, “Di gi tal Integrated Ci rcui ts”, PHI,
2003.

[10]Sung
-
Mo Kang and Yusuf Lebl ebi ci, “CMOS
Di gi tal Integrated Ci rcui ts”, TMH, 2003

[11]Mohammad Sha
ri fkhani, “Desi gn and Anal ysis of
Low
-
Power SRAMs”, PhD Thesi s, Uni versi ty of
Waterl oo, 2006.

[12]

Bharadwaj S. Amrutur “Desi gn And Anal ysis Of
Fast Low Power SRAMs”

August 1999

[13]Ingvar Carlson, “Desi gn and Eval uati on of Hi gh
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dvanced
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[14]Andrei S. Pavl ov,


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[15] Tegze.P.Haraszti, “CMOS Memory Ci rcui ts”,
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