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Nov 2, 2013 (3 years and 11 months ago)

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45

Chapter 3

Miller Operational Amplifier


The designs of all three op
-
amp topologies are subject to the following
constraints:


Table 3
-
1
. Low power CMOS op
-
amp design constraints

These constraints were chosen to meet specifications

of typical op
-
amps
employed in low
-
power applications while considering limitations set by the fabrication
process to be used as well as the topologies themselves.

3.1

Schematic Design and Implementation of the Miller Op
-
amp

The design of the 2
-
stage or M
iller op
-
amp was handled by both members of the
group. However, owing to the 2
-
stage nature of this topology, the design process would
be simplified if each stage is sized independently. The design of the differential amplifier
(1
st

stage) was handled by N
eil Michael Axalan while the design of the common source
amplifier (2
nd

stage) was done by Alfonso Cesar Albason.

An issue that arose from this method of independent sizing is matching the DC
output voltage of the first stage with the DC input voltage of
the second stage. The DC
output voltage of the first stage is crucial in the design of the second stage because it
serves as the bias of the second stage. Therefore, the design of the second stage must be
delayed until such time that an approximate value o
f the DC output voltage has been
acquired. Once this is finished, the sizing of each stage can proceed independently.

One major consideration in the design of the op
-
amps is the minimum length that
is to be used for all transistors included in the design.
This is actually the first step in the
design process. The fabrication process to be used can support up to a minimum length of
0.24um. To use the process to the fullest, the minimum length possible was first used.
This is because there is no literature av
ailable indicating the gain achievable using a
length of 0.24um with the Miller op
-
amp topology. However, as we will find out later,
the minimum gain requirement of 15,000 cannot be achieved without driving at least one
of the transistors out of saturation

while using the minimum length. It is essential that at
zero AC input condition, all of the transistors are in saturation to ensure linear operation,
thus minimizing distortion, once a small signal input differential voltage is applied. The
techniques to
increase the gain will be discussed later.


46


After setting the length to be used in sizing, each member of the group determined
the right combination of transistor widths for each stage that would achieve the design
constraints. The methodology in determini
ng the transistor widths will be discussed by
each member for the particular stage assigned to him. For the design of the differential
amplifier, see Section 3.1.1 and for the design of the common source amplifier, see
Section 3.1.2. Lastly, for stability,

a compensating capacitor is designed in Section 3.1.3.

3.1.1

Schematic Design and Implementation of the Differential Amplifier


Shown in Figure 3
-
1 is the schematic of the differential amplifier, the first stage
of the 2
-
stage or Miller op
-
amp topology. A
lso shown in the figure are the transistor
labels that will be used throughout the discussion.


Figure 3
-
1
. Schematic diagram of a differential amplifier


Take note of the bulks of all transistors being connected to either
V
dd

or
g
nd

only.
This is dictated by the fabrication process. In other processes, it is possible to connect the
bulks to the sources. Also, take note of the subcircuit on the lower left portion of Figure
3
-
1 and is boxed in Figure 3
-
2. This is a balun circuit and
is used to convert a single
voltage source into a differential voltage, which is the necessary input for the differential
amplifier. The inductors are from the
xfmr

device from the
analogLib

library with a
primary
-
to
-
secondary ratio of 2:1. This circuit is

not part of the Miller op
-
amp topology
but is used here to simplify the testing process. Also, the input transistors have been
selected to be PMOS transistors because of the higher rejection of noise that is achieved
with the use of input PMOS transistors
. However, speed is sacrificed in the process. In
this design, speed, which is measured through slew rate, is not a constraint, and therefore
is a parameter that can be traded off for noise rejection. Although noise performance is

47

also not a constraint, mo
re applications give higher premium on noise rejection as
compared to speed.

In designing the op
-
amp, the circuit designer has control over the current, width,
length, and bias voltages of the various elements of the circuit. Since the topology was
alread
y chosen, the bias voltages have already been indicated in the topology. It would
seem that most of the bias voltages needed are set by current mirrors. For a current mirror
to effectively mirror the current from one leg to the other, it is good practice t
o use the
same aspect ratio for the two transistors. Therefore, in the schematic, the transistors are
grouped into pairs as shown in Figure 3
-
3. These pairs of transistors should have equal
ratios to reduce the mismatch between the currents through them.
That leaves the widths
and currents to vary. The range of currents available for use is limited by the maximum
power requirement of 2.5mW. Since we are given a supply voltage of 2.5V, the
maximum total current that can be drawn from the supply is 1mA. Also
, assuming 10
current branches from the supply voltage forming the actual op
-
amp, with each branch
carrying the same current, the maximum supply bias current is 100uA. Giving some
allowance so as not to exceed this value and considering the fact that the g
ain of the
Miller op
-
amp is inversely proportional to the current through the op
-
amp, the supply
bias current was selected to be 10uA. Although the op
-
amp could be designed with a
lower bias current and theoretically, with a higher voltage gain due to this

lower bias
current, it is the first time that the laboratory has designed analog circuits with very low
bias currents. Therefore, proper operation with this low current bias is not guaranteed,
much less with even lower bias currents. The bias current just

chosen is valid for
transistors PM2 and PM3 of Figures 3
-
1 to 3
-
3. However, from PM2, the current
branches out to two branches. For matching, the currents in these two branches have been
set to be equal.


Figure 3
-
2
. Schematic dia
gram of a Differential amplifier with the balun circuit boxed


48


Figure 3
-
3
. Schematic diagram of the differential amplifier with paired transistors

Therefore, in the case of PM0, PM1, NM0 and NM1, the bias current is set to
5uA. Hen
ce, the widths of the transistors are varied to achieve the specifications. For the
design of the differential amplifier, the initial sizes have been computed from the
MOSFET current equation in the deep saturation region given in Equation 3
-
1.


Equation 3
-
1.
Current equation in the deep saturation region

where

I
D

is the transistor current

k’ is the transconductance parameter with a typical value of
for
PMOS transistors and

f
or NMOS transistors,

W is the transistor width,

L is the transistor length,

V
GS

is the gate
-
to
-
source voltage, and

V
T

is the threshold voltage of the transistor.

As a first approximation, the (
V
GS
-
V
T
) parameter called the overdrive voltage,
V
OV
, is set at
0.17V. This value was acquired from initial simulations done with
arbitrarily chosen transistor widths and is valid for all transistors in this design. Applying
the constants and solving for W for different combinations of transistor types and bias
current
s, we acquired the initial sizes of the transistors. Following this methodology,
examples of calculating transistor widths are illustrated at the next page.


49




This method for calculating the transistor

widths was employed for all the
transistors. After acquiring all the initial transistor widths, the schematic was simulated
and tested if it has achieved the target specifications. (For the details on running a
simulation of the DC Voltage Gain and gettin
g various transistor parameters, see Section
3.3.) In designing for the 15K gain, it is necessary to achieve a slightly higher gain so that
at the desired gain of 15K, the circuit has a decent output voltage swing. The magnitude
of the necessary output vol
tage swing is dependent on the application upon which the op
-
amp is to be used. The output swing dictates the type of devices that can be driven by the
op
-
amp. Thus, overshooting the gain is a necessity for the op
-
amp to be useful.

For the design of the re
sistor, assuming a voltage of 1.8V across the drain and
source terminals of PM3, and from the bias current of 10uA previously chosen, these
result to a resistance of 180K ohms. This resistance is relatively big leading to a very
large area in the layout im
plementation. To reduce the area of the overall circuit, the
resistor could be implemented using diode
-
connected transistors. However, in the initial
tests and simulations, not having finalized values for the widths of the transistors, it is
very difficult

to size the diode
-
connected transistors. Thus, until at least an estimate of the
possible ranges of the widths of the transistors has been acquired, the resistor will not be
implemented as diode
-
connected transistors. It is also not advisable to defer the

sizing of
the diode
-
connected transistors up to the very last step for they may significantly affect
the carefully sized transistor widths of the other transistors in the circuit. Thus in this
design, after the initial testing and simulations, the diode
-
c
onnected transistors were sized
using the graphical method as outlined in Section 3.1.2. Briefly, a diode
-
connected
transistor is biased with a
V
gs
=
V
ds

of 1.8V. Setting the length to be equal to 1.2um for the
other transistors, the width is swept and the c
urrent through the transistor is plotted. From
this plot, the width that corresponds to the desired current of 10uA is the width to use. If
there is no width that corresponds to the desired current, another diode
-
connected
transistor is placed in series wi
th the previous transistor and the simulation is run again.
This is done until such time that a width corresponds to the desired current. Following
this methodology for this design, the needed current cannot be obtained using a single
diode
-
connected trans
istor. Therefore, two same
-
sized, diode
-
connected transistors, each
transistor having a width of 900nm, were implemented to generate the desired current.

After simulating and testing the design, the acquired parameters are compared
with the constraints if
the specifications have been met. Also, the operating
-
point

50

parameters of all the transistors in the design must be checked if these parameters fall
within allowable limits. These operating
-
point parameters include the current,
V
ds
,
V
dsat
,
(
V
ds
-
V
dsat
),
V
gs
,
V
th

and overdrive voltages. The overdrive voltages, given by the
expression (
V
gs
-
V
th
), state how conductive the channel through which the carriers pass
through is. This parameter must be greater than zero. The same is true for the circuit
parameter (
V
ds
-
V
dsat
). This quantity states how saturated the transistor is. Note that the
current equation used in computing for the initial transistor widths is valid for transistors
operating in the deep saturation region. In the case that all the parameters meet the
constraints and fall within the limits, then the layout implementation of the design is
done. However, if not all specifications are met, then one solution is to check the
overdrives of the transistors and compare it with the assumed overdrive of 0.17V. Th
is
can be achieved by varying the widths of the transistors. In general, increasing the
transistor width decreases the
V
dsat
’s of the transistors but decreases the
V
OV
. A small
value for a transistor’s
V
dsat

is desirable because the output voltage swing re
quires that a
minimum voltage be allotted for keeping the transistor in saturation. Therefore, the
degree by which the transistor is ON, which is proportional to
V
OV
, forms a trade off with
V
dsat
.

In this design, after the initial sizes have been fed into

the schematic, all of the
parameters including the operating
-
point parameters were recorded. Since this is just the
initial sizing, the non
-
idealities of the equations used to compute the transistor widths
surface. These non
-
idealities, resulting primaril
y from short
-
channel effects, cause some
of the parameters to go beyond the specified limits, which is the case for most overdrives
and (
V
ds
-
V
dsat
)’s. Afterwards, each pair of transistors that has to be of the same width is
varied and the corresponding ef
fects on the operating
-
point parameters and DC gain are
recorded. This suggests which transistor pair widths to vary once a parameter goes
beyond the suggested limits. (For the details on the results from this procedure step, see
Chapter 5). Since DC gain
is the primary consideration, the widths were varied to
maximize the gain while keeping all of the operating
-
point parameters within limits.
Once the maximum gain is achieved while keeping all of the operating
-
point parameters
within limits and this gain s
till does not meet the specifications, another solution is to
modify the topology. This can be done by adding gain
-
boosting circuits, if for example
the parameter not met is gain. Another possible solution is to use another design
methodology other than th
e one outlined here. An alternative methodology is the one
employed by [18]. This methodology was also tried for this op
-
amp design. Although it
achieved a higher gain than the methodology just employed, the designers found it
difficult to saturate all of
the transistors. When finally all of the transistors were saturated,
the gain is lower than the gain achieved with the design using initial sizes derived from
equations. This may be attributed to the fact that in the alternate methodology, the bias
circuit
s were separately designed. In our design, the bias circuits were incorporated into
the topology through the use of the current mirrors whose widths have been constrained
to be equal (or an integer multiple of the other) for matching.

Lastly, another poss
ible solution is to increase the transistor length. This step is
the most convenient to perform but is considered as the last resort since it would mean
that the given constraints cannot possibly be achieved using the fabrication process, the
topology empl
oyed and the length used. The trend is to miniaturize components, which
can be achieved by using the minimum length that could possibly be handled by the

51

process. If the transistor length is increased, then the process made available by the
technology is n
ot maximized. However, since all of the other possibilities stated above to
achieve the constraints are not enough, this would seem to be the last resort. During our
design, we reached this last step several times, first at L = 240nm, then at 500nm, 800nm,

and 1um. Finally, at L = 1.2um, we were able to achieve the specified constraints. In each
iteration of the transistor’s length, all of the steps outlined in this design methodology
were carried out. For the 1.2um length, the widths shown in Table 3
-
2 hav
e been
computed and alongside are the final widths after tweaking. The widths of the diode
-
connected transistors implemented to replace the resistor are also included. These sizes
result from the graphical sizing methodology as outlined in Section 3.1.2. T
he case cited
in Section 3.1.2 is the design of a diode
-
connected transistor to replace the bias resistor
for the common source amplifier. However, the same methodology was applied in the
differential amplifier resistor bias and the result is included here

for completeness.


Table 3
-
2
. Comparison between computed and simulated transistor widths

Shown in Figure 3
-
4 is the final schematic diagram of the differential amplifier
stage of the Miller op
-
amp with diode
-
connected transistor
s forming the resistor bias.
This circuit, when connected to the 2
nd

stage common source amplifier achieves
approximately 21.5K of DC gain and a power consumption of 779uW.


Figure 3
-
4
. Final schematic diagram of the differential am
plifier


52

The circuit parameters of the design schematic using the initial transistor sizes
(2
nd

column of Table 3
-
2) are given in Table 3
-
3. For comparison, the circuit parameters
of the design schematic using the final transistor sizes are given in Table 3
-
4.


Table 3
-
3
. Parameters of circuit using initial transistor sizes


Table 3
-
4
. Parameters of circuit using final transistor sizes

It should be noted that for convenience, the values for PMOS transistors

indicated
in all tables included in this design are negated values of the actual values in the
simulations.

It can be seen from a comparison of Table 3
-
3 and Table 3
-
4 that although the
operating
-
point parameters are within limits, the currents in Table
3
-
4 are closer to the
desired currents of 5uA for NM0, NM1, PM0, and PM1, and 10uA. This would imply
that the bias of the final design schematic is matched with the transistor sizes to give out
the required transistor behavior that will result to the requi
red gain.







53

3.1.2

Design and Implementation of the Common Source Amplifier

Shown in Figure 3
-
5 is the basic topology of a common source amplifier. An ideal
current source was first used to set the current requirement of the amplifier. It must be
careful
ly noted that the voltage where the common source amplifier achieves its highest
gain should be the point where the differential amplifier also attains its largest voltage
gain. This voltage should be the input to the common source amplifier. This design
c
onsideration will maximize the op
-
amp’s gain when the two stages are cascaded.


Figure 3
-
5.

Common source amplifier topology

A resistor having a value of 1 mega ohm was placed in parallel to the ideal current
source to approximate
the behavior of the actual current mirror that will eventually
replace the ideal current source. As discussed above, a PMOS transistor was used
because of its high noise rejection property, trading stability for speed. Sizing was done
by first setting the
lengths of the CMOS amplifier to minimum. The output of the circuit
was plotted as shown in Figure 3
-
6, while sweeping the input voltage of the circuit. The
DC sweep is performed while varying the width and current passing through the
transistor simultaneo
usly. This process is achieved by using the parametric analysis of the
simulation tool. The sizes and values were chosen so that the gain corresponds to the
voltage where the differential amplifier attains its largest value, which is not necessarily
the hi
ghest gain the circuit can attain. The circuit may have a higher gain but if the input
voltage does not correspond to the point where the first stage attains its highest gain, then
that gain is not chosen.





54

Figure 3
-
6.

Output voltage family of curves


Getting the derivative of this family of output curves, we have a family of gain
curves. From these curves, we choose the curve that has its highest maximum gain
approximately where the previous stage achieves its highest gain, as shown in Figure 3
-
7.

Figu
re 3
-
7.

Common source amplifier gain curves with varying widths and currents



55

In establishing the width and the current needed to achieve the gain of the circuit,
the operating
-
point parameters have to be double
-
checked. All transistors should have
been dr
iven into saturation and must have decent voltage overdrive values. From the
current requirement of the circuit, the current mirror can be designed. This current mirror
makes up the bias circuitry of the common source amplifier, effectively replacing the
i
deal current source as shown in Figure 3
-
8. The current mirror is implemented using
NMOS transistors. The widths of both NM0 and NM1 are set equal to improve matching
between transistors. The transistor lengths used must be the same for the entire circuit.

Another ideal current source was used, this time to set the current that will pass through
the current mirror. The value of this current must be the same as the current chosen from
the previous simulated results. Varying the widths of the NMOS transistor
s, the output of
the circuit was graphed. Another family of output curves was generated. The gain curve
that has its highest gain corresponding to the voltage where the first stage achieves its
highest value is chosen. Both NMOS transistors must be checked

if they properly mirror
the current in both legs of the topology. If design constraints, especially gain and power
are not met, then resizing of transistors is deemed necessary.


Figure 3
-
8.

Common source amplifier with active load

using an ideal current source

By using an active load, a high
-
impedance output load can be realized without
using excessively large resistors or a large power
-
supply voltage. As a result, for a given
power
-
supply voltage, a larger voltage gain can be achi
eved using an active load than
would be possible if a resistor were used for a load. The resistive load approach also
greatly increases the power dissipation. However, it should be mentioned here that for a
low
-
gain, high frequency stages, it may be desira
ble to use resistor loads (if they do not
require much silicon area) because they often have less parasitic capacitances associated
with them.



56

After determining the NMOS widths and current needed to achieve the required
gain specification of the circuit
, the voltage across the current source was determined.
This voltage is the supply voltage minus the drain to source voltage,
V
DS
, of the NMOS
transistor, (
V
DD
-
V
DS
). The
V
DS

of the NMOS transistor can be viewed in the simulation
tool’s results browser. Thi
s measured voltage across the resistor, V
RES,

over the current,
V
RES
/I, will be used to determine the resistance employed to model the ideal current
source as can be seen in Figure 3
-
9 below.

Figure 3
-
9.

Common source amplifier with active load using a res
istor

To decrease the area of the amplifier in its layout implementation, the resistor was
realized using a transistor. This diode connected PMOS transistor, shown in Figure 3
-
10
was sized by plotting the current passing through the resistor versus the pos
sible widths
of the transistor. From the plot shown in Figure 3
-
11, the width was chosen so the
corresponding current passing across the transistor is the same current passing through
the transistor.

The supply voltage minus the
V
DS

of NM5, will be used a
s the voltage across the
resistor or effectively also the
V
DS

that will be used in sizing the PMOS diode connected
transistor as resistor. Thus the complete working schematic of the common source
amplifier as shown in Figure 3
-
12 is achieved.








57


Figure 3
-
10.

Diode connected transistor as resistor sizing

Figure 3
-
11.

Current versus width plot




58


Figure 3
-
12.

Final schematic diagram of the differential amplifier


Table 3
-
5.

Compari
son between computed and simulated transistor widths

Some transistor sizes were changed without the necessity of redesigning or
simulation. This change will make the layout implementation more convenient. Resizing
will make the transistor fingers equal to
or a factor of each other and will make the
transistors easier to interdigitate. As this is done, the operating
-
point parameters must be
checked, not to sacrifice performance for ease of implementation.




59


Table 3
-
6
. Parameters of

circuit using final transistor sizes

3.1.3

Schematic Design and Implementation of the Compensating
Capacitor

Although there are no specifications for the AC response of the system, which the
compensating capacitor improves, this capacitor is an essential
component for the proper
function of any 2
-
stage system because of its feedback factor. When uncompensated, this
system has the tendency to be unstable leading to oscillatory operation and if the
magnitude of the feedback increases (the feedback builds up)
, may eventually destroy the
op
-
amp and the devices connected to them. The compensating capacitor introduces an
additional pole away from the initial gain and phase margin frequency. This causes the
magnitude to dip earlier and consequently, results in a l
ower transition frequency.
However, with a lower transition frequency, the phase at that earlier frequency has not
descended much provided that the pole introduced by the compensating capacitor is much
earlier than the natural poles of the circuit. Since t
he phase has not yet descended that
much compared to the rate of descent of the magnitude plot, at the new cutoff frequency,
a higher phase margin is achieved. This results to an op
-
amp with lower bandwidth
throughout the range of frequencies of its operat
ion.

Figure 3
-
13 shows the location of the compensating capacitor in the schematic
diagram of the Miller op
-
amp. A first order approximation in computing the value of the
compensating capacitor is given by Equation 3
-
2.


Equation

3
-
2.
Approximate compensating capacitance calculation

where GB refers to the gain
-
bandwidth product/transition frequency/cutoff
frequency, and


g
m

refers to the transconductance of the output transistor PM4.

However, this value of compensating capacitor o
nly results in a phase margin of
45


and a cutoff frequency of 88MHz. (For the details on how the values here were
acquired, see Chapter 4.) A phase margin of at least 60


is recommended in the design to
ensure that the circuit is stable. By varying this c
apacitance and getting the phase margin
for every variation made, a capacitance value of 5pF yields a phase margin of 81


and a
cutoff frequency of 2.55MHz, meeting the minimum phase margin requirement. The
complete Miller op
-
amp topology design satisfying

the design constraints and having

60

operating
-
point parameters that fall within the suggested limits is shown in Figure 3
-
13.
A flowchart of the design methodology for the differential amplifier of the Miller op
-
amp
topology assuming that the topology was a
lready chosen is shown in Figure 3
-
14.


Figure 3
-
13
. Location of the compensating capacitor for the miller op
-
amp




61

Figure 3
-
14
. Flowchart of the design methodology of the differential amplifier

Acquire design specifications

Simplify topology (transistor grouping)

Choose current satisfying constraints

Set uniform transistor length

Compute for initial transistor widths

Compute for bias resistance

Simulat
e and extract parameters

Compare characteristics with constraints

Check operating point parameters

Determine operating point parameter
sensitivity on transistor group variations

Adjust widths of transistor groups
affecting unacceptable parameters

Change unif
orm transistor length

Implement resistor as diode
-
connected
transistor/s

Gain achieved?

Fi
nal characterization

N

Y


62

The transistor widths used for the

2
-
stage op
-
amp topology are presented in Table
3
-
7 while the circuit parameters are presented in Table 3
-
8. The power consumption is
found to be 748.4uW (See Section 3.3 on the calculation details).


Table 3
-
7
. Transistor widths
of the 2
-
stage op
-
amp schematic


Table 3
-
8
. Parameters of the 2
-
stage op
-
amp circuit

3.2

Layout Design and Implementation of the Miller op
-
amp

Upon completion of the schematic design and implementation of the Miller op
-
amp, the im
plementation of the physical layout of the schematic follows. Since the
electrical characteristics of a certain circuit are closely coupled with the physical layout,
the following layout strategies have been adapted to minimize the undesirable effects of
m
ismatch, parasitics, and electromigration:



Routing within the circuit was minimized.



Guard rings were made as close as possible to transistors.



Routing one metal over another was avoided as much as possible to minimize
parasitic capacitances since a capaci
tor is formed by two overlapping metal
layers.


63



The number of contacts/vias was maximized to ensure that two surfaces
supposed to be in contact are indeed in contact.



A consistent routing direction was followed as much as possible, with metal 2
being used f
or horizontal routing and metal 3 for vertical routing.



The width used in routing the metal layers was 0.6um instead of the minimum
width of 0.4um for metal layers 2 to 5 and 0.32um for layer 1.



A vertical parallel
-
plate implementation of the capacitor was

employed to
reduce the area.

3.2.1

Layout Design and Implementation of the NMOS Transistors

In laying out the various elements of the design, the first step taken was to
determine if there is a common factor among all of the transistor widths. Having a
co
mmon factor from the transistor widths would make the layout much easier.
Unfortunately, for this design there is none. By inspection, we can easily say that there is
no common factor for 580nm, 900nm, and 3um. Next, the greatest common factor among
the tr
ansistor widths is determined. In our case, if NM0 and NM1’s width of 580nm were
600nm, these two transistors’ width would have a common factor with the width of NM2
and NM3 (each of 900nm width). However, one problem with this is that the common
factor is

300nm. In our process, the minimum allowable transistor width is 580nm.
Another possibility would be to increase 580nm to 600nm and 900nm to 1.2um making
the common factor to be 600nm, which is higher than the minimum. This would translate
to a per
-
finger

width of 600nm for transistors NM0 to NM3. Nonetheless, although the
width of 3um has 600nm as a common factor with the other two “new” widths, this
would translate to 5 fingers for NM4 and NM5. Although an odd number of fingers is
alright, mixing odd wit
h even number of transistors is not good because of the
consequent difficulty in routing. This is due to the fact that for symmetry, the centers of
each row of transistors should be along a single vertical line as illustrated in Figure 3
-
15.
Hence, the gat
es, sources and drains are not aligned. As a solution to this, a per
-
finger
width for NM4 and NM5 that is closest to the other fingers and that is 750nm is adapted.
Then, transistors with different per
-
finger widths are placed in different rows. This can b
e
achieved by placing the 4 fingers of NM4 at row 1, the 4 fingers of NM5 at row 3 and the
rest of the transistors having a uniform per
-
finger width of 600nm at row 2 as shown in
Figure 3
-
16. The adjusted transistor widths and their finger sizes are as fol
lows:


Table 3
-
9
. Comparison of schematic sizing and layout sizing transistor widths



64







Figure 3
-
15
. Illustration of odd and even fingering








Figure 3
-
16
. Layout floorplan for the NMOS transistors

The floorplan in Figu
re 3
-
16 is the actual floorplan implemented in the layout of
the NMOS transistors. The individual strips of labeled with a number each represent a
particular finger of an NMOS transistor with the exception of the unlabeled strips at the
end of each row, wh
ich represent dummy transistors. These dummy transistors are
necessary to improve matching by providing the same boundary conditions for all of the
transistors involved in the circuit operation. However, before proceeding with the actual
layout, the adjust
ments made to the sizes of some transistors were reflected to the
schematic, simulated and checked if the constraints and recommended limits on the
operating
-
point parameters were still satisfied. Although some of the operating
-
point
parameters changed sig
nificantly, these parameters still fall within the acceptable range
and so, the floorplan in Figure 3
-
16 was carried out.

.2.2 Layout Design and Implementation of the PMOS Transistors


Table 3
-
10
. Comparison of schematic sizing and layout sizing transistor

widths


65

Having attained these widths, the size of transistor PM4 was changed so it will
have the same width as that of transistors PM2 and PM3. This change is also necessary so
the width of PM4 is a factor of transistors PM0, PM1 and PM5, making it easier
to
interdigitate them. From inspection, one can conclude that each transistor can be divided
into exactly 9 um finger widths. However, the “10 micron rule” would dictate that
clustering is necessary to ensure that guard ring contacts are within 10 um of ea
ch other.
Using 6 um finger widths would have odd number of fingers for transistors PM0, PM1
and PM5. This is avoided since it is very difficult to layout transistors with odd number
of fingers, especially when interdigitated with even numbered transistor
fingers.
Interdigitation would be nearly impossible if one is to maintain symmetry, which is
highly considered in analog IC CMOS layout. Changing finger widths to 4.5 um ensures
that guard ring contacts are within 10 um from other supply contacts. The need

for
clustering and thus additional dummies is also eliminated. The final layout floorplan of
the PMOS transistors is shown in Figure 3
-
17.







Figure 3
-
17
. Layout floorplan for the PMOS transistors

3.2.3

Layout Design and Implementation of the Compensa
ting Capacitor

As what has been observed in theses done previously at the laboratory, the
capacitor occupies a large area. Because of the major role that the capacitor plays in the
stability of the op
-
amp it must be included in the circuit. Nonetheless, re
ducing the area
that it occupies would be very desirable. Implementing the capacitor as an external
component is an option, but external capacitors are not accurately matched with the
needed capacitance of the op
-
amp and may not serve their purpose that we
ll.
Furthermore, other mismatch effects not inherent with the monolithic implementation of
capacitors may surface, complicating the overall response of the op
-
amp.

Fortunately, the very topic of monolithic op
-
amp implementation has been tackled
in a gradua
te thesis. Several implementations have been presented that reduce the area
occupied by the capacitor. Among these, the vertical parallel
-
plate capacitor using
minimum width metal layers was chosen because of the relative simplicity in
implementation given

the reduction in area that it provides. The details of implementing
the capacitor can be found in [19]. In brief, Figure 3
-
18 shows an example of a vertical
parallel
-
plate capacitor. To achieve the required capacitance of 5pF, as indicated in Table
3
-
11,
108 strips of each metal layer from 3 to 5 were laid out, each 105.4um long, and
0.46um wide.


66


Table 3
-
11
. Minimum width, vertical parallel
-
plate capacitor parameters

Where n refers to the number of strips of a terminal sandwiched

between two
strips of the opposite terminal

N refers to the number of strips

(a)

(b) Top view


Figure 3
-
18
. Example of a vertical parallel
-
plate capacitor using three metal laye
rs

and 6 strips. (a) Isometric view (b) Top view

After determining the necessary changes to the transistor widths to address the
various layout issues, the changes were reflected on the schematic. Then, this schematic
was tested before proceeding to the a
ctual layout of the individual transistors to check if
the constraints are still met despite the changes made. Table 3
-
12 compares the widths
found after the design phase with the widths of the transistors ready for layout. Table 3
-

67

13 shows the circuit par
ameters of the design schematic after the changes to the transistor
widths have been reflected. From Table 3
-
13, the power consumption was found to be
766.48uW.


Table 3
-
12
. Comparison of transistor widths before and after consid
ering layout issues


Table 3
-
13
. Parameters of the schematic to be laid out

After the complete 2
-
stage schematic of Figure 3
-
13 was laid out, the layout was
tested against the gain and power constraint. After performing the tests,

it was found out
that the gain and power consumption was more or less the same as that acquired in the
testing of the schematic with transistor sizes as shown in Table 3
-
12. Table 3
-
14 shows a
summary of the gain and power consumption of the 2
-
stage op
-
am
p at different stages in
the design process.


68


Table 3
-
14
. Summary of gain and power consumption of the op
-
amp

at different stages in the design process

3.3

Testing

In this section, the details in conducting the various tests to d
etermine the circuit
parameters such as gain and power consumption will be explained.

3.3.1

Gain

As explained in Section 3.1.1, a balun circuit, as illustrated in Figure 3
-
2, is
attached to the circuit to convert single voltage sources to voltage differenc
es (differential
voltages). As can be seen in Figure 3
-
19, a balun circuit has two voltage sources, which,
in this case are labeled
V
ic

and
V
id
.
V
ic

is commonly known as the common
-
mode input
voltage while
V
id

is the differential
-
mode input voltage. The te
rm
gain

that is commonly
used in this design refers to the differential
-
mode voltage gain
A
v,dm

which is actually the
ratio of the change in the output voltage
V
od

with respect to a change in the differential
-
mode input voltage
V
id
. The equation form of th
e differential
-
mode voltage gain is given
by Equation 3
-
3.


Equation 3
-
3.
Differential
-
mode voltage gain

On the other hand,
A
v,cm

refers to the common
-
mode voltage gain, which is the
ratio of the change in the output voltage
V
oc

with respect to a change in the common
-
mode input voltage
V
ic
. The equation form of the common
-
mode voltage gain is given by
Equation 3
-
4.


Equation 3
-
4.
Common
-
mode voltage gain

It is actually
A
v,dm

that is referred to by the te
rm gain in the specifications of the
op
-
amp design (i.e.
A
v,dm

must be greater than 15K).

To measure
A
v,dm
,
V
ic

is initially set at a constant value. Then a DC analysis is
setup with
V
id

as the variable to be swept.
V
id

is varied typically from a few negat
ive
millivolts to a few millivolts for differential input circuits such as the differential
amplifier in Section 3.1.1. In the case of non
-
differential input circuits such as the
common
-
source amplifier in Section 3.1.2,
V
id

is swept from

V
dd

to
+V
dd
. For

this
analysis, the single
-
ended output voltage is selected as the output. After plotting the
output voltage, the derivative of this output trace is evaluated. In the resulting waveform,

69

any value along the curve is the value of the differential
-
mode volta
ge gain at that
particular differential
-
mode input voltage and the set
V
ic
. It is the minima for inverting
amplifiers and maxima for non
-
inverting amplifiers that is compared with the given
minimum gain constraint which in this case is 15K.

3.3.2

Operating
-
point Parameters


To extract the value of the operating
-
point parameters of the circuit, an operating
-
point analysis is performed after setting the value of the design variables present in the
circuit to correspond to the intended operating point. Then ea
ch value of the operating
-
point parameter can be determined by looking up the parameter expression in the Results
Browser and evaluating the expressing through the calculator. This is done for every
parameter of every transistor that is present in the circ
uit.

3.3.3

Power Consumption

To determine the power consumption of the op
-
amp, the total current drawn from
V
dd

is multiplied by
V
dd
. The equation form of the power consumption is given by
Equation 3
-
5.


Equation 3
-
5.
Power consu
mption

To illustrate, given the schematic in Figure 3
-
13, and the data in Table 3
-
13, we
first add the currents through PM2, PM3, PM4, and PM5. These currents correspond to
the last four rows in the second column of Table 3
-
13 namely: 12.88uA through PM2,
13.31uA through PM3, 138uA through PM4, and 142.4uA through PM5. These currents
sum up to 306.59uA being sourced from
V
dd
. The total current is then multiplied by 2.5 to
determine the power consumed by the op
-
amp, which in this case is 766.48uW.