Abstract

amountdollElectronics - Devices

Nov 2, 2013 (4 years and 8 days ago)

96 views

Mohmmad Alam

Wayne Buckhanan

Hubert George

IC Fab. Lab 4

Report
_Process.

Abstract



This report shows

the explanation of the
N
MOS process
for fabricating the layout
designed in the previous project
.
The idea is to show the steps of fabrication and the
corr
esponding numbers for each stage.

Process:


The objective

of th
is

report is t
o

sp
e
c
if
y each of the steps of the process
t
hat will be used to
fabricate our devices. Although, the first fabrication will be the diodes, all the other parameters
for the other d
evices will be shown.

For the diodes fabrication is needed masks number I (Active area definition), mask III


(Contact
holes) and mask IV


(Metal pattern).

The p
-
n diodes are expected to have large reverse
breakdown voltage due to the light doping in th
e p region.
All the necessary calculations

such as
breakdown voltages and drive in numbers for the process

are specified on the calculations
section.

For the transistors and inverters, w
e decided to use two different gate oxide thicknesses to
reach the tw
o threshold voltages for the two types of transistors (Enhancement and Depletion)
used for the design. To obtain the different thicknesses it is necessary to add an additional mask

(mask

number

V


Depletion mode gate oxide)
. Then,
to achieve each thic
knes
s we need to

grow

an initial gate oxide layer, and then open

a window for the active areas of our depletion mode
transistors
.

Finally,

grow the remaining gate oxide for the enhancement mode transistors while
growing the full gate oxide for our depletion mo
de transistors.

For the actual gate oxidation the
TransLC
step was not taken into account, although,

t
he TransLC is used to
reduce the sodium ion
contamination of the furnace we are going to be really careful with our procedure.


MOS Capacitors,

Ring Oscil
lators, Ohmic Contacts and Gated Hall Bar will be fabricated
in the

same process.

They do not play any
role in the parameters calculation.


Itemized
Fabrication Process:


1.

Grow first oxide (Pad oxide)
: This first oxide is grown for protecting the Silicon f
rom the
Nitride that will be deposited in step

2.

Recipe “IC_FirstOxide” on furnace.


-

RCA Clean

-

Furnace: 1000 ˚ C


20 min
utes
,

d
ry O2


30 min
utes
, h
igh N2.

Approximately 300 Ǻ.

3.

Deposit Nitride (Thanks TAs)

-

Approximately 1000 Ǻ.

4.

Lithography.
(
Mask I



Active area definition)

5.

Nitride
Etch
and Oxide removal
(
D
ry etch
using RIE
: “ICnitrd process” for IC Fab
) (Fig
1
a)

6.

Grow field oxide

(Thermal Oxidation)

(Fig 1
b)
.

6b).

-

RCA Clean

-

Furnace: 1100 ˚ C


654 minutes, dry O2
. Approximately
4226
Ǻ is grown
.

(More than
2000

Ǻ

is good
)
.

7.

Nitride
removal (Wet etching in H3PO4

for 2


3 hours
)

8.

Oxide removal

(Wet etch in
B
HF

for 60 seconds
)

(Fig 1
c)

9.

First
gate oxide
growth
(
Initial enhancement mode gate

o
xi
de).

-

RCA Clean

-

Furnace: 1100 ˚ C


41 minutes, dry O
2.
Approximately 987 Ǻ

is grown
.

10.

Lithography (Mask V


Depletion mode gate oxide)

11.

Etch depletion mode active area windows
(Wet etch

in BHF

and check un
til S
ilicon is
reached
)

12.

Second gate oxide growth (Gate oxides)

(Fig 1
d)

-

RCA Clean

-

Furnace: 1100 ˚ C



1 minute, dry O2. Approximately 96 Ǻ on etched area

is grown for
depletion mod
e transistors

and 1000 Ǻ on enhancement mode transistors area.

13.

Deposit Polysilicon layer

(Thanks again TAs)

Approximately 3000 Ǻ.
(Fig 1
e)

14.

Lithography. (Mask II


Poly patte
rn)

15.

Etch

Polysilicon (Dry etch using RIE: Using “ICpoly” recipe for IC Fab)

(Fig 1
f)

16.

Phosphorous diffusion (Thermal Furnace)

17.

R
emove P2O5 glass

(Wet etch in BHF
)

(Fig 1
g)

18.

Active area d
rive in (Thermal Furnace)
.
see Fig 3.

-

RCA Clean

-

Furnace: 925 ˚ C


20 minute, N2.

Na = 1X10
16
cm
-
3

Nd = Approximately 4x10
19
cm
-
3

19.

Deposit Silicon Dioxide
Inter
-
level dielectric (
PECVD
:
“sio2dep” for IC Fab
)

(Fig 1
h)

approximately

3000 Ǻ is deposited.

20.

Lithography

(
Mask III


Contact holes
)

21.

Etch

Silic
on Dioxide
from contact holes
(Dry etch using RIE
: “ICvia” for IC Fab
)

(Fig
1
i)

22.

Deposit metal layer (Sputter
Al
uminum Silicon
. Approximately 2000 Ǻ
)

(Fig
1
j)

23.

Lithography (Mask IV


Metal pattern).

24.

Etch
metal
(Dry etch using RIE
: “ICAlEtc
h
” for IC Fab
)

(Fig

1
k)

25.

Anti
-
c
orrosion
treatment

(Immersion in DI water for 10 minutes)

26.

Final
anneal
.


See Figure
1

for the process flow cross
-
sections.



Figure
1

Cross
-
sectional view of various stages of our f
abrication
p
rocess




Figure
2

Threshold
voltages

as a functi
on of gate oxide thickness with an acceptor doping
of 10
16

cm
-
3


Calculations:


Calculations for diode
breakdown voltage

(using
empirical relationship
i
)



Calculation for drive times, oxide thicknesses other parameters are in the exc
el file attached with
the soft copy.


-

Enhancement mode with gate oxide thickness of 1000 Ǻ and
expected to

have
a V
T
of 0.72 V

-

Depletion mode gate oxide thickness100 Ǻ with a V
T
of

approximately

0.1 V.

-

Wafer acceptor concentration 1X10
16
cm
-
3






i

S.M. Sze and G. Gibbons, “Avalanche Breakdown Voltages of Abrupt and Linearly Graded p
-
n Junctions in Ge,
Si, GaAs, and GaP,” Appl. Phys. Lett. 8, 111 (1966)