Bernardo B. Carvalho

actuallyabandonedElectronics - Devices

Nov 15, 2013 (3 years and 8 months ago)

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17th TM on Research Using Small Fusion Devices

Real
-
Time Digital Systems for Control on Small Tokamaks

Presented by:

Bernardo B. Carvalho

Association Euratom/IST
on behalf of the

CFN Data Acquisition Group
and ISTTTOK Team


17th TM on Research Using Small Fusion Devices

Introduction:Traditional Architectures


Small tokamaks usually rely on

pre
-
programmed waveforms for open
-
loop
control of plasma parameters

Tokamak:

Sensor

(Magnetics)

Sensor

(Interferometry)

Waveform

Generator #1

Actuator

(Power Suplies)

Actuator

(Gas Puffing)

Waveform

Generator #2

DATA

ACQUISITION

SYSTEM

“Trial
-
and
-
error” type
operation

Hard to get similar
discharges, as the plasma is
a multivariable complex
system

Reprogram of waveforms is
normally an
empiric

and
lengthy task


Data acquired needs to be
correlated
manually

against
control waveforms

17th TM on Research Using Small Fusion Devices

Plasma Control


Plasma close
-
loop control on medium/small
tokamaks example:

Tokamak

Sensor

(Magnetics)

Actuator

(PSU)

Sensor

(Pressure/

Interferometry)


Single
-
Input Single
-
Output
(SISO)
ANALOG

controllers


Not easily Re
-
configurable


Hard to Optimize


Allows only simple control
schemes (e.g PID)


Control of Plasma
Parameters is NOT coupled!

Actuator

(Gas Puffing)

Controller #1

(PID)

Controller #2

(PID)

Sensor X

Actuator Y

Controller #

(PID)

17th TM on Research Using Small Fusion Devices

Recent digital technologies and

tools developed at IST enable a New Paradigm

LOCAL
CONTROL
PROCESSOR
D
.
AC
Q
UNITS
D
.
AC
Q
UNITS
ACTUATOR
CONTROL
REMOTE
PARTICIPATION
TOKAMAK
PLASMA
1
/
10
Gb Ethernet
Db SERVER
D
ATA
AC
Q
UNITS
REAL TIME
NETWORK
Sensors
/
Diagnostics
CENTRAL
CODAC
PSU
GAS
PUFFING
FW
FAST SWITCH UNIT

Integrated
Digital Control System,
Sensors
-
to
-
Actuator
, based on available low
-
cost
technologies

General Purpose Processors: Intel,
PowerPC…

Open
-
Source Standards and Real
-
Time
Operating Systems: XML, CORBA, SQL,
RTAI

DSP
-

Digital Signal Processors

FPGA
-

Field Programmable Gate Arrays


MIMO

Multiple Input
-

Multiple Output Controller


Dedicated
real
-
time synchronous network

for
event and timing distribution

17th TM on Research Using Small Fusion Devices

Application: The ISTTOK Plasma Control



PCI
-
TR
-
512 Acq. & Control Module


8 Diff. Channels @14 bit/

2 Msamples /sec

Galvanic Isolated.

512 Mbytes of SDRAM


Synchronization of clock and trigger
among boards (Master
-
Slave)

Integrated FPGA and DSP for data
processing

Digital output for Control Purposes

See Poster 26

ISTTOK Plasma Control System



12 Magnetic Probes on a poloidal circular section



Fast position determination code running on DSP
(128
μ
s
)

using 8 signals



Two PWM controlled PSU for Vertical and Horizontal
Equilibrium Fields



Data transmitted to PSU by optical connection

17th TM on Research Using Small Fusion Devices

Next Step: Upgrade of ISTTOK Plasma Control

Present ISTTOK Tomography Diagnostic:


Three pinhole camera


Each camera with 10 active channels


Two different reconstruction methods

Fourier
-
Bessel Algorithm (Faster ~40
μ
s
)

Neural
-
Network (~400
μ
s
)


Reconstruction algorithms running and tested
on a standard PC with RTAI OS

See Poster P13

Goal: Multi
-
Diagnostic Plasma Control System



Magnetic reconstruction using 12 probes(+), Vloop and Rogoswky coil



Tomography reconstruction used when magnetic reconstruction fails to give
reliable results ( e.g. during current inversion in AC operation)

HFS

LFS

17th TM on Research Using Small Fusion Devices

New system overview

GAS
INJECTION
Gateway
Local Processing Node
(
ATX Motherboard
/
PCIe
)
WWW
Ethernet
1
/
10
Gb Switch
Digitizer Boards
ATCA Chassis
FIRESIGNAL SERVER
POWER SUPPLIES
\
Low Cost
Controling Module
(
dsPIC
)

RS
485
\
Low Cost
Controling Module
(
dsPIC
)

RS
485
POSTGRES
SQL SERVER
17th TM on Research Using Small Fusion Devices

ATCA
-
Based System

Why ATCA?

Reliable mechanics (serviceability, shock and vibration)

High security and regulatory conformances

Highly configurable

Robust power infrastructure and large cooling capacity (200W per board)

Ease of integration of multiple functions and new features

Supports 14 slots in 19” cabinet or
smaller versions


Ability to host multiple controllers and storage on a shelf

17th TM on Research Using Small Fusion Devices

ATCA Backplane Topologies

Advanced ATCA Interface Topologies


DUAL
-
STAR BACKPLANE

FULL MESH BACKPLANE

Multi
-
protocol support for interfaces up to 20 Gb/s

Each slot is interconnected through up to four 2.5 Gb/s links with an
actual throughput capacity of ~800 MByte/s per link

Scalable aggregated shelf capacity to 2.5Tb/s

17th TM on Research Using Small Fusion Devices

Low
-
Cost ATCA

Controller
-
Processor Module

ATCA™
Processor Blade
ix
86
Intel®
multi
-
core
NORTH
+
SOUTH
bridges
DDR
2
DRAM
10
GB
/
s
PCIe
slot
Gbit
Ethernet
port
RS
-
232
port
ATM
Add
-
on
card
X
16 8
GB
/
s FDX
PCIe
switch
PCIe
switch
X
8 4
GB
/
s FDX
X
16 8
GB
/
s FDX
12
ATCA
channels
(
2
to
13
)
X
4 2
GB
/
s FDX
each
ATCA
power
ATCA Fabric channel
PCIe
switch
X
16
PCIe
female
connector
7
-
2
13
-
8
X
8 4
GB
/
s FDX
8
GB
/
s
8
.
5
GB
/
s
ATCA™
Processor Blade

Based on a PC plain
ATX Motherboard

with PCIe, assembled on a specially designed
ATCA

Carrier Board

Any Processor in the ix86 multi
-
core family

Easily upgraded to higher processing power

Processing power over 40 GFLOPS and a set of SIMD instructions

Plain Linux or Real
-
time OS (RTAI)


Connected to the PCI Express


switch fabric of the ATCA™ carrier

by an
×
16 full
-
duplex link (8 GB/s) directly from its Northbridge


Occupies 2 slots of the ATCA shelf

17th TM on Research Using Small Fusion Devices

ATCA 32
-
Channel Digitizer Module

32
x Clock
X
4
PCI Express
TM

2
GB
/
s
Xilinx
Virtex
4
FX
60
/
FX
100
FPGA
ATCA
TM
digitizer
/
(
waveform generator
)
Main board
DDR
2
SODIMM
512
MB
RS
-
232
11
x Aurora
TM

500
MB
/
s
Gbit optical
8
x GPIO
8
x EIA
-
485
RTM connector
ATCA Fabric
connector
carrier board
connector
64
x GPIO
Front panel
status
/
ctrl
ATCA
TM
power
connector
ATCA
TM
update
channel
&
clocks
connector
IPMC
timing

32
Analogue differential Inputs


±
32V dynamic range, 18
-
bit resolution


Anti
-
aliasing filters and Galvanic isolation


Simultaneous sampling at 2 MHz

programmable Decimation down to


1 kHz on the FPGA


Optional I/O Rear Transition Module:

8 analogue 16
-
bit/50MSPS

8 digital input/output channels


(EIA
-
485)

1 fiber optic port


(x1 full
-
duplex 500 MB/s) SFP

RS
-
232 interface


Developed for JET Vertical Stabilization
Enhancement Project EP2

ATCA
TM
Digitizer
/
Waveform Generator carrier board
ATCA
TM

leds
32
x Clock
64
x GPIO
Front panel
status
/
ctrl
Channel
32
ATCA
TM

Front Panel
Signal
conditioning
Reset
main board
Connector
4
x DB
37
connector
32
x isolated
differential
analog
Input
±
32
v
ADC
18
-
bit
2
MSPS
1
kV
Isolation
Channel
2
Channel
1
ADC module
Signal
conditioning
1
kV
Isolation
ADC
18
-
bit
2
MSPS


Digitizer

Main board




Digitizer

Carrier


board



A

T

C

A


B

U

S

Optional

RTM

I/O

ATCA MODULE

17th TM on Research Using Small Fusion Devices

ATCA FAST Data Acquisition Module

Sync
Ref CLK
Analog inputs
4
-
7
ATCA
TM

Backplane
ATCA Fabric
Connector
PCI EXPRESS
SWITCH
Pex
8516
Analog inputs
0
-
3
Clock
Synthesis
Xilinx
TM
FPGA
Virtex
4
XC
4
VFX
60
-
10
FF
1152
DDR
2
1
GB or
2
GB
4
x
13
bits
100
MHz
Clock
Synthesis
Analog
-
to
-
Digital
Converter
Block
4
-
channels Block
#
1
4
-
channels Block
#
2
Update channel
&
cloks
connector
4
x
ATCA clock
ATCA Power
Connector
IPMB HA
IPMC
channels
3
-
12
channels
1
-
2
5
x
1
x Aurora
4
x
MGTs
4
x
MGTs
4
x PCIe
2
GB
/
s
48
V
ATCA Compliant
200
W Power Input
Module
12
v
Analog Power
Digital Power

ATCA Digitizer Module 8 channel with up to

250 MS/s@13bit


High Power FPGA


Multi
-
rate filtering based on events


Local Control algorithms


Can Implement PHA and data reduction in
real
-
time


Developed for JET Gamma Ray Spectroscopy
Enhancement Project
EP2

17th TM on Research Using Small Fusion Devices

Digital Link for the Actuators

ATCA SHELF REAR PANELS
S
F
P
DIGITAL
LINKS
2
.
5
Gbit
/
s
ANALOGUE
OUTPUTS
DIGITAL
IO
(
RS
485
)
S
F
P
DIGITAL
LINKS
2
.
5
Gbit
/
s
ANALOGUE
OUTPUTS
DIGITAL
IO
(
RS
485
)
SFP
D
I
N
4
1
6
1
2
62
.
5
/
125
um
Duplex
Optical Fiber
BUFFERS
XILINX
VIRTEX
2
FPGA
T
3
P DIGITAL LINK CARD
Controller sub
-
rack
D
B
9
D
I
N
4
1
6
1
2
RS
-
485
INTERFACE CARD
OGSL
Option
EHSL
Option
DB
-
37
to DB
-
9
RS
-
485
cable
BUFFERS
dsPIC
μ
P
TP3
-

Hard real
-
time communications protocol for Trigger, Timing and data
Transport

(Developed under JET Vertical Stabilization Enhancement EP2 Project)

OGSL
-

Optical gigabit serial link



Transmits the control signals to the actuator
units, enough to attain low loop delays (< 1us).




Developed for JET Vertical Stabilization
Enhancement Project



Fiber optic SFP LC
-
Duplex connector (850 nm
over 62.5/125 μm fiber)



Full
-
duplex communications with
programmable signaling rate from 622 Mbaud to
3.125 Gbaud

EHSL
-

Electrical high
-
speed serial link



2/4 wire RS
-
485 (ANSI TIA/EIA
-
485
-
A)



Up to 8 half
-
duplex or 4 full
-
duplex channels on
a 37 pin D
-
sub connector



Programmable signaling rate up to 30 Mbaud

17th TM on Research Using Small Fusion Devices

Firmware Tools


Hardware Level


FPGA
: Data Reduction, Pulse Processing, Timing, Event Detection and Distribution


VHDL, Verilog, (in future directly SCILAB, MATLAB, etc)


DSP
: Fast plasma position determination and PID control algorithms


C, Assembly


dsPIC
: PWM control of PSU


Assembly

Example 1: Block Diagram of
real time

sampling decimation

.....
BLOCK
#
8
BLOCK
#
2
BLOCK
#
1
64
BIT TIME TRIGGER REGISTER
DSP EMIFA
ADDRESS
AND
CONTROL
DUAL
-
PORT RAM
8
X
(
2
x
256 16
-
bit words
)
INTERRUPT LOGIC
DSP INTERRUPTS
FPGA XC
3
S
2000
2
MHz clk
SYNCHRONIZATION LOGIC
CONTROL LOGIC
TIMING LOGIC
INTERFACE LOGIC
ADC SERIAL
DATA
DSP EMIFA
64
-
BIT DATA
16
bit De
-
SERIALIZER
DECIMATION FIR
(
8

)
DECIMATION FIR
(
8

)
3
:
1
MU
X
32
MHz clk
TRIGGER
SYNC
8
DECIMATION BLOCKS
Example 2: Block Diagram of
real time

PHA Implementation in FPGA

for

Gamma Ray Spectroscopy

17th TM on Research Using Small Fusion Devices

Software Tools


Local Processor Node


RTOS
: Real time multi
-
diagnostic reconstruction and control algorithms


RTAI, C / C++


FIRESIGNAL

“Node”: Data storage, parameter programming and integration in
the general control and acquisition system (FIRESIGNAL SERVER)


C++ Code/ CORBA


Event Based


Configuration data described in XML format


Standardized hardware description

17th TM on Research Using Small Fusion Devices

Summary



Small tokamaks are adequate platforms to develop Control and Data
Acquisition Systems using State
-
of
-
Art digital technologies and tools
(PCIe, ATCA, RTAI, XML)


IST/CFN’s future work will build on previous developments towards
ITER relevant solutions


New machines (or enhancements of the existent) represent crucial
opportunities to explore new concepts compatible with ITER
requirements with benefits to the ITER CODAC Specification


Common remote collaboration tools and unified data description
methods will boost collaboration between Labs