VLSI Design Digital Systems and VLSI

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27 Νοε 2013 (πριν από 4 χρόνια και 1 μήνα)

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VLSIDesign
DigitalSystemsandVLSI
1
DigitalSystemsandVLSI
SomayyehKoohi
DepartmentofComputerEngineering
SharifUniversityofTechnology
Adaptedwithmodificationsfromlecturenotespreparedby
author
Overview

WhyVLSI?

ICManufacturing

CMOSTechnology
ModernVLSIDesign:Chap12of38
SharifUniversityofTechnology

TheVLSIdesignprocess
WhyVLSI?
1.
Lowercost

chiparea

numberofICs,…
2
.
Faster
ModernVLSIDesign:Chap13of38
SharifUniversityofTechnology
3.
Lowerpowerconsumption
4.
Higherreliability

Moreintegrationlessintra-chipconnectionsbetter
reliability

Bettertestabilit
5.
Lessdesignandfabricationtime
ICsoverDiscreteCircuits

Advantages

Size

Speed

Fastercommunication
ModernVLSIDesign:Chap14of38
SharifUniversityofTechnology

PowerConsumption

Smallerparasiticcapacitance&resistance

Manufacturingcost

Costreductionforpartsotherthanchip(supply,fan,PCB,…)

ASICmightbemoreexpensivethanstandardIC,butsystem’scost
willbelower
VLSIandyou

Processors:

personalcomputers

Electronicsystemsincars
ModernVLSIDesign:Chap15of38
SharifUniversityofTechnology

Entertainmentsystems,…

DRAM/SRAM

Special-purposeprocessors
LevelsofIntegration

SSIMSILSIVLSI

Criteria:

Gatecount(2-20,20-200,200-2000,2000+)
ModernVLSIDesign:Chap16of38
SharifUniversityofTechnology

Pincount

Featuresize

Chipsize

Function

gate&FF,module,subsystem,system
LevelsofIntegration(cont’d)

WheretogoafterVLSI?

ULSI(UltraLargeScaleIntegration-whichisbetween
500,000and10,000,000transistors),

GSI
(GiganticScaleIntegration
-
whichisover
10
,
000
,
000
ModernVLSIDesign:Chap17of38
SharifUniversityofTechnology
(gg
transistors).
Overview

WhyVLSI?

ICManufacturing

CMOSTechnology
ModernVLSIDesign:Chap18of38
SharifUniversityofTechnology

CMOSTechnology

TheVLSIdesignprocess
Technology

RawmaterialofICManufacturing:Silicon
Wafers

Duringmanufacturing
ModernVLSIDesign:Chap19of38
SharifUniversityofTechnology
gg

Photolithographicprocess:patternonmask(layout)
patternonwafer

Changingthemaskwithasinglefabricationline
differentICs

Differencebetweenfabricationtechnology:
typeoftransistorused

Bipolar,nMOS,CMOS
CMOSTechnology
ModernVLSIDesign:Chap110of38
SharifUniversityofTechnology

Bipolar,nMOS,CMOS

Differentspeed&powercharacteristics(tradeoff)
Moore’sLaw

GordonMoore(co-founderofIntel)predicted
thatnumberoftransistorsperchipwouldgrow
exponentially(doublesevery18months)
log(#dev)
t
ModernVLSIDesign:Chap111of38
SharifUniversityofTechnology

ObstaclesforMoore’slaw:
1.
QuantityandvarietyofproductswhichuseICshashadlessprogress
2.
Costofdesignverificationandtestislarge
3.
Complexityofdesignmakesitdifficulttomanageitamongdesignand
engineeringgroups

RoleofCADtools
t
Moore’sLawplot
s
10
7
10
8
integrated
10
9
ModernVLSIDesign:Chap112of38
SharifUniversityofTechnology
year
#transistors
10
0
10
1
10
0
10
2
10
0
10
3
10
4
10
5
10
6
memory
CPU
1970
1960 1980 1990
integrated
circuit
invented
2000
2010
Costoffabrication

Currentcost:$2-3billion

Typicalfablineoccupiesabout1cityblock,
employsafewhundredpeople
ModernVLSIDesign:Chap113of38
SharifUniversityofTechnology
employsafewhundredpeople

Mostprofitableperiodisfirst18months-2
years
CostfactorsinICs

Forlarge-volumeICs

packagingislargestcost

testingissecond
-
largestcost
ModernVLSIDesign:Chap114of38
SharifUniversityofTechnology

testingissecond
largestcost

Forlow-volumeICs

designcostsmayswampallmanufacturingcosts

Wafersize:8inch(12inch)

Chipsize:1.5x1.5cm2
Overview

WhyVLSI?

ICManufacturing

CMOSTechnology
ModernVLSIDesign:Chap115of38
SharifUniversityofTechnology

CMOSTechnology

TheVLSIdesignprocess
TheVLSIdesignprocess

Canbepartoflargerproductdesign

Majorsteps

specification
ModernVLSIDesign:Chap116of38
SharifUniversityofTechnology
p

Algorithmdesign

architecture

logicdesign

circuitdesign

layout(physicaldesign)
Thesteps

Specification

Function(whattodo)

Cost

Otherrequirements

Architecture:largeblocks

Logic
ModernVLSIDesign:Chap117of38
SharifUniversityofTechnology

Logic

Gates

Latches

Flip-Flops

Circuits

transistorEstimatespeed&power

Layout

Layoutsizedeterminesfabricationcost

Shapesdetermineparasiticsthecircuitspeedandpower
ChallengesinVLSIdesign
1.
Multiplelevelsofabstraction
Englishspecification
executablebehaviorsystemthroughput,
programdesigntime
function
function
c
c
ModernVLSIDesign:Chap118of38
SharifUniversityofTechnology
sequentialregister-functionunits,
machinestransferclockcycles
logicgateslogicliterals,gatedepth
transistorscircuitnanoseconds
rectangleslayoutmicrons
unction
unction
cost
cost
ChallengesinVLSIdesign
(cont’d)
2.
Multipleandconflictingcosts

Speed

Area

Cost
ModernVLSIDesign:Chap119of38
SharifUniversityofTechnology

power,…
3.
Shortdesigntime
(6monthsdelaylosing33%oftheprofit)
Solutions

Techniquestoeliminateunnecessarydetail:
1.
Hierarchicaldesign

Divideandconquer:breakingthechipintoahierarchyofcomponents,
whereeachconsistsofabodyandanumberofpins
2.
Designabstraction
Ultilllfbtti
ModernVLSIDesign:Chap120of38
SharifUniversityofTechnology

Usemultiplelevelsofabstraction
3.
UsingCADtools:triestosolveallthe3mentionedproblems
1.
Dealingwithmultiplelevelsofabstractioniseasierwhenyouarenot
absorbedinthedetails
2.
Computerprogramscananalyzecosttrade-offsmuchbetter
3.
Computersaremuchfasterthanhumans
CADToolsCategories
1.
Designentrytools(e.g.,schematiccapture)

Captureadesigninmachine-readableformforusebyother
programs

Don’tdoanyrealdesignwork
2
.
Analysisandverificationtools(e.g.,spice)
ModernVLSIDesign:Chap121of38
SharifUniversityofTechnology
y(g,p)

Easetheanalysistask

Don’ttellhowtochangethecircuitforthedesiredfunction/spec.
3.
Synthesistools(e.g.,Leonardo)

Createadesignatalowerlevelofabstractionfromahigherlevel
description.

Bothhierarchicaldesignanddesignabstractionareas
importanttoCADtoolsastheyaretohumans
Dealingwithcomplexity

Divide-and-conquer:limitthenumberof
componentsyoudealwithatanyonetime

Groupseveralcomponentsintolarger
ModernVLSIDesign:Chap122of38
SharifUniversityofTechnology
components:

Transistorsformgates

Gatesformfunctionalunits

Functionalunitsformprocessingelements


Hierarchicalname

Interiorviewofacomponent

Componentsandwiresthatmakeitup

Exteriorviewofacomponent=type:
ModernVLSIDesign:Chap123of38
SharifUniversityofTechnology

body

pins
Full
adder
a
b
cin
sum
cout
Instantiatingcomponenttypes

Eachinstancehasitsownname:

add1(typefulladder)

add2(typefulladder)
ModernVLSIDesign:Chap124of38
SharifUniversityofTechnology

Eachinstanceisaseparatecopyofthetype:
Add1(Full
adder)
a
b
cin
sum
cout
Add2(Full
adder)
a
b
cin
sum
Add1.a
Add2.a
Ahierarchicallogicdesign
b
1
b
2
ModernVLSIDesign:Chap125of38
SharifUniversityofTechnology
z
box
1
box
2
x
Netlistsandcomponentlists

Netlist:
net1:top.in1in1.in
net2:i1.outxxx.B
topin
1
:topn
1
xxxxin
1

Componentlist:
top:in1=net1n1=topin1
n2=topin2n3=topine
out=outnet
ModernVLSIDesign:Chap126of38
SharifUniversityofTechnology
topin
1
:top.n
1
xxx.xin
1
topin2:top.n2xxx.xin2
botin1:top.n3xxx.xin3
net3:xxx.outi2.in
outnet:i2.outtop.out
i1:in=net1out=net2
xxx:xin1=topin1
xin2=topin2xin3=botin1
B=net2out=net3
i2:in=net3out=outnet
Componenthierarchy
top
ModernVLSIDesign:Chap127of38
SharifUniversityofTechnology
i1
xxx
i2
Hierarchicalnames

Typicalhierarchicalname:

top/i1.foo
ModernVLSIDesign:Chap128of38
SharifUniversityofTechnology
component
pin
Layoutanditsabstractions

Layoutfordynamiclatch:
ModernVLSIDesign:Chap129of38
SharifUniversityofTechnology
Stickdiagram
V
DD
ModernVLSIDesign:Chap130of38
SharifUniversityofTechnology
Q
'
D
V
SS

'
Transistorschematic
'
+
ModernVLSIDesign:Chap131of38
SharifUniversityofTechnology
D
Q'

Mixedschematic
D
Q'
'
ModernVLSIDesign:Chap132of38
SharifUniversityofTechnology
D
Q'

inverter
Circuitabstraction

Continuousvoltagesandtime:
+
ModernVLSIDesign:Chap133of38
SharifUniversityofTechnology
t
v
t
v
Digitalabstraction

Discretelevels,discretetime:
full
cout
sum
a
t
a
sum
ModernVLSIDesign:Chap134of38
SharifUniversityofTechnology
adder
cin
sum
b
full
adder
cout
cin
sum
a
b
t
b
t
a
t
b
t
t
sum
Register-transferabstraction

Abstractcomponents,abstractdatatypes:
0010
ModernVLSIDesign:Chap135of38
SharifUniversityofTechnology
+
+
0010
0001
0100
0011
Top-downvs.bottom-updesign

Top-downdesignaddsfunctionaldetail

Createlowerlevelsofabstractionfromupper
levels
Btt
ditbttif
ModernVLSIDesign:Chap136of38
SharifUniversityofTechnology

Bottom
-
updesigncreatesabstractionsfrom
low-levelbehavior

Gooddesignneedsbothtop-downandbottom-
upefforts
Designvalidation

Validation:Anytechniquewhichincreasesconfidence
incorrectness,e.gsimulation

Verification:Formalproofofcorrectness

Mustcheckateverystepthaterrorshaven’tbeen
ModernVLSIDesign:Chap137of38
SharifUniversityofTechnology
introduced

Thelongeranerrorremains,themoreexpensiveitbecomes
toremoveit

Forwardchecking:compareresultsofless-andmore-
abstractstages

Backannotation:copyperformancenumberstoearlier
stages
Manufacturingtest

Notthesameasdesignvalidation:justbecause
thedesignisrightdoesn’tmeanthateverychip
comingoffthelinewillberight
Mtiklhkhthfti
ModernVLSIDesign:Chap138of38
SharifUniversityofTechnology

Mustquicklycheckwhethermanufacturing
defectsdestroyfunctionofchip

Mustalsospeed-grade

Todeliverhighquality:Makethechipdesigner
responsiblefortesting