Semiconductor Manufacturing Technology

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© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Semiconductor
Manufacturing Technology


Michael Quirk & Julian Serda

©
October 2001 by Prentice Hall


Chapter 16



Etch




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Objectives

After studying the material in this chapter, you will be able to:

1.

List and discuss eight important etch parameters.

2.

Explain dry etch, including its advantages and how etching
action takes place.

3.

List and describe the equipment systems for seven dry
plasma etch reactors.

4.

Explain the benefits of high
-
density plasma (HDP) etch and
the discuss the four types of HDP reactors.

5.

Give an application example for dielectric, silicon and metal
dry etch.

6.

Discuss wet etch and its applications.

7.

Explain how photoresist is removed.

8.

Discuss etch inspection and important quality measures.




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Applications for Wafer Etch in CMOS Technology

Photoresist

mask

Film

to be etched

(a) Photoresist
-
patterned substrate

(b) Substrate after etch

Photoresist

mask

Protected

film

Figure 16.1



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Process Flow in a Wafer Fab

Implant

Diffusion

Test/Sort

Etch

Polish

Photo

Completed wafer

Unpatterned
wafer

Wafer start

Thin Films

Wafer fabrication (front
-
end)

Used with permission from Advanced Micro Devices

Figure 16.2



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Process

Categories of Etch Processes


Wet Etch


Dry Etch


Three Major Materials to be Etched


Silicon


Dielectric


Metal


Patterned Etch Versus Unpatterned Etch




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Parameters


Etch rate


Etch profile


Etch bias


Selectivity


Uniformity


Residues


Polymer formation


Plasma
-
induced damage


Particle contamination and defects




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Rate


T

Start of etch

End of etch

t = elapsed time during etch


T = change in thickness

Figure 16.3



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Wet Chemical Isotropic Etch

Isotropic etch
-

etches in all
directions at the same rate

Substrate

Film

Resist

Figure 16.4



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Anisotropic Etch with Vertical Etch Profile

Anisotropic etch
-

etches
in only one direction

Resist

Substrate

Film

Figure 16.5



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Sidewall Profiles for Wet Etch Versus Dry Etch

Table 16.1



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Bias

(b)

Bias

Substrate

Resist

Film

(a)

Bias

Resist

Film

Substrate

W
b

W
a

Figure 16.6



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etching Undercut and Slope

Undercut

Substrate

Resist

Film

Overetch

Figure 16.7



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Selectivity

S =

E
f

E
r

E
f

Nitride

Oxide

E
r

Figure 16.8



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Uniformity

Measure etch rate at 5 to 9 locations on
each wafer, then calculate etch
uniformity for each wafer and compare
wafer
-
to
-
wafer.

Randomly select 3 to 5 wafers in a lot

Figure 16.9



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Polymer Sidewall Passivation for
Increased Anisotropy

Plasma ions

Resist

Oxide

Polymer formation

Silicon

Figure 16.10



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Dry Etch


Advantages of Dry Etch over Wet Etch


Etching Action


Potential Distribution




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Advantages of Dry Etch over Wet Etch

Table 16.2



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Plasma Etch Process of a Silicon Wafer


8)

By
-
product
removal


1)

Etchant gases
enter chamber

Substrate

Etch process chamber


2)

Dissociation of
reactants by
electric fields


5)

Adsorption of
reactive ions
on surface


4)

Reactive +ions
bombard surface


6)

Surface reactions of
radicals and surface film

Exhaust

Gas delivery

RF generator

By
-
products


3)

Recombination of
electrons with atoms
creates plasma


7)

Desorption of
by
-
products

Cathode

Anode

Electric field

l

l

Anisotropic
etch

Isotropic etch

Figure 16.11



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Chemical and Physical Dry Etch
Mechanisms

Reactive +ions
bombard surface

Surface reactions of
radicals + surface film

Desorption of
by
-
products

Anisotropic etch

Isotropic etch

Sputtered surface
material

Chemical Etching

Physical Etching

Figure 16.12



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Chemical Versus Physical

Dry Plasma Etching

Table 16.3



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Schematic View of Reactor Glow
Discharge with Potential Distribution

Plasma (+V
p
)

Ion
sheath

RF

Powered electrode (V
t
)

Grounded electrode

-
V 0 +V

V
p

V
t

Figure 16.13



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Effects of Changing Plasma Etch Parameters

Table 16.4



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Plasma Etch Reactors


Barrel plasma etcher


Parallel plate (planar) reactor


Downstream etch systems


Triode planar reactor


Ion beam milling


Reactive ion etch (RIE)


High
-
density plasma etchers


Etch System Review


Endpoint Detection


Vacuum for Etch Chambers




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Typical Barrel Reactor Configuration

Vacuum pump

Gas in

RF electrode

RF

generator

Wafers

Quartz boat

Wafers

Reaction chamber

Figure 16.14



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Parallel Plate Plasma Etching

Roots
pump

Process gases

Exhaust

Gas
-

flow controller

Pressure controller

Gas panel

RF generator

Matching
network

Microcontroller
Operator Interface

Gas dispersion
screen

Electrodes

Endpoint signal

Pressure signal

Roughing

pump

Wafer

Figure 16.15



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Schematic of a Downstream Reactor

Plasma chamber

Diffuser

Wafer chuck

Heat lamp

To vacuum system

Microwave energy

Microwave source

2.45 MHz

Figure 16.16



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Triode Planar Reactor

Inductively
-
coupled

RF generator (3.56 MHz)

Capacitively
-
coupled

RF generator (100 kHz)

Induction coil

Capacitor

Figure 16.17



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

General Schematic of Ion Beam Etcher

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

_

Hot filament
emits electrons

Gas inlet

(Argon)

To vacuum system

Neutralizing filament

Accelerating grid

Screen grid

Electromagnet
improves ionization

Plasma chamber

(+anode repels +ions)

Wafer can be tilted to
control etch profile

Redrawn from

Advanced Semiconductor Fabrication Handbook
, Integrated Circuit Engineering Corp., p. 8
-
12.

Figure 16.18



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Parallel Plate RIE Reactor

RF generator

Wafer

Powered
electrode

(cathode)

Grounded
electrode

(anode)

Ar
+

(physical etch
component)

F

(chemical etch
component)

Figure 16.19



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

High Density Plasma Etcher

Photograph courtesy of Applied Materials, Metal Etch DPS

Photo 16.1



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Schematic of Electron Cyclotron Reactor

Microwave source 2.45 MHz

Wave guide

Diffuser

Quartz window

Electrostatic chuck

Cyclotron magnet

Plasma chamber

Wafer

Additional magnet

13.56 MHz

Vacuum system

R
edrawn from Y. Lii, “Etching,”
ULSI Technology
, ed. by C. Chang & S. Sze, (New
York: McGraw
-
Hill, 1996), p. 349.

Figure 16.20



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Inductively Coupled Plasma Etch

Electromagnet

Dielectric
window

Inductive coil

Biased wafer chuck

RF generator

Bias RF generator

Plasma
chamber

R
edrawn from Y. Lii, “Etching,”
ULSI Technology
, ed. By C. Chang and S. Sze (New York:
McGraw
-
Hill, 1996), p. 351.

Figure 16.21



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Dual Plasma Source (DPS)

Decoupled plasma
chamber

Turbo pump

Lower chamber

Cathode

Wafer

Capacitively
-
coupled
RF generator

(bias power)

Inductively
-
coupled
RF generator

(source power)

Redrawn from Y. Ye et al,
Proceedings of Plasma Processing XI
, vol. 96
-
12, ed. by G. Mathad and
M. Meyyappan (Pennington, NJ: The Electrochemical Society, 1996), p. 222.

Figure 16.22



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Magnetically Enhanced Reactive Ion Etch
(MERIE)

Electromagnet
(1 of 4)

13.56 MHz

Biased wafer chuck

Wafer

Redrawn from
Wet/Dry Etch

(College Station, TX: Texas Engineering Extension Service, 1996), p. 165.

Figure 16.23



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Dry Etcher Configurations

Table 16.5



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Endpoint Detection for Plasma Etching

Endpoint
detection

Normal etch

Change in etch
rate
-

detection
occurs here.

Endpoint signal
stops the etch.

Time

Etch Parameter

Figure 16.24



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Characteristic Wavelengths of Excited
Species in Plasma Etch

Table 16.6



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Endpoint Detection

Photograph courtesy of Advanced Micro Devices, Lam Rainbow etcher

© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Dry Etch Applications


Dielectric Dry Etch


Oxide


Silicon Nitride


Silicon Dry Etch


Polysilicon


Single
-
Crystal Silicon


Metal Dry Etch


Aluminum and Metal
Stacks


Tungsten Etchback


Contact Metal Etch




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Requirements for Successful Dry Etch

1.

High selectivity to avoid etching materials that
are not to be etched (primarily photoresist and
underlying materials).

2.

Fast etch rate to achieve an acceptable throughput
of wafers.

3.

Good sidewall profile control.

4.

Good etch uniformity across the wafer.

5.

Low device damage.

6.

Wide process latitude for manufacturing.




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Dry Etch Critical Parameters

Equipment Parameters
:


Equipment design


Source power


Source frequency


Pressure


Temperature


Gas
-
flow rate


Vacuum conditions


Process recipe





Other Contributing Factors
:


Cleanroom protocol


Operating procedures


Maintenance procedures


Preventive maintenance schedule

Process Parameters
:


Plasma
-
surface
interaction:


-

Surface material


-

Material stack of


different layers


-

Surface temperature


-

Surface charge


-

Surface topography


Chemical and physical
requirements


Time


Quality Measures:


Etch rate


Selectivity


Uniformity


Feature profile


Critical dimensions


Residue

Plasma
-
etching

a wafer

Figure 16.25



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Oxide Etch Reactor

CF
4


C
3
F
8


C
4
F
8


CHF
3


NF
3


SiF
4


Ar

Wafer

Electrostatic chuck

Plasma

Selection of fluorocarbon
and hydrocarbon chemicals

HF

CF
2

F

CHF

CH
4

Figure 16.26



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Etch Stop Hard Mask Layer

Example: Silicon nitride, Si
3
N
4
, serves as etch
-
stop during LI oxide etch.

Note: The numbers show the order of the five operations.

Figure 16.27



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Contact Etching to Varying Depths

Contact holes

S

D

G

Figure 16.28



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Polysilicon Conductor Length

Polysilicon gate

Gate oxide

The gate length determines
channel length and defines
boundaries for source and drain
electrodes.

Drain

Source

Gate

Figure 16.29



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Polysilicon Gate Etch Process Steps

1.

Breakthrough step to remove native oxide
and surface contaminants

2.

Main
-
etch step to remove most polysilicon
without damage to gate oxide

3.

Overetch step to remove remaining
residues and poly stringers while
maintaining high selectivity to gate oxide




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Undesirable Microtrenching during
Polysilicon Gate Etching

Substrate

Poly

Resist

Gate oxide

Ions

Trench in gate oxide

Figure 16.30



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Silicon Trench Etching

Figure 16.31



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Major Requirements for Metal Etching

1.

High etch rates (>1000 nm/min).

2.

High selectivity to the masking layer (>4:1),
interlayer dielectric (>20:1) and to underlying layers.

3.

High uniformity with excellent CD control and no
microloading (<8% at any location on the wafer).

4.

No device damage from plasma
-
induced electrical
charging.

5.

Low residue contamination (e.g., copper residue,
developer attack and surface defects).

6.

Fast resist strip, often in a dedicated cluster tool
chamber, with no residual contamination.

7.

No corrosion.




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Metal Stack for VLSI/ULSI Integration

Figure 16.32



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Typical Steps for Etching Metal Stacks

1.

Breakthrough step to remove native oxide.

2.

ARC layer etch (may be combined with above step).

3.

Main etch step of aluminum.

4.

Overetch step to remove residue. It may be a
continuation of the main etch step.

5.

Barrier layer etch.

6.

Optional residue removal process to prevent
corrosion.

7.

Resist removal.




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Tungsten Etchback

Metal
-
2 stack

(d) Metal
-
2 deposition

Tungsten

plug

(a) Via etch through ILD
-
2 (SiO2)

Metal
-
1 stack

ILD
-
2

ILD
-
1

Via

SiO
2

(c) Tungsten etchback

SiO
2

Tungsten

plug

(b) Tungsten CVD via fill

Tungsten

Figure 16.33



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Wet Etch


Wet Etch Parameters


Types of Wet Etch


Wet Oxide Etch


Wet Chemical Strips




© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Wet Etch Parameters

Table 16.7



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Approximate Oxide Etch Rates in BHF
Solution at 25


C

Table 16.8



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Historical Perspective
-

Polysilicon Etch Technology Evolution

Table 16.9



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Photoresist Removal

Plasma Ashing


Asher Overview


Plasma Damage


Residue Removal





© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Atomic Oxygen Reaction with Resist in Asher

Substrate




Resist

Asher reaction chamber

2) O
2

dissociates into
atomic oxygen

3) Plasma energy
turns oxygen
into + ions

4) Neutral O and O
+

react with
C and H atoms in resist

Neutral oxygen
radicals

5)

By
-
product
desorption

6)

By
-
product removal

Exhaust

Gas delivery

Downstream
Plasma

1) O
2

molecules
enter chamber

+

+

+

+

+

+

+

l

l

+

Figure 16.34



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Post Etch Via Veil Residue

Via veils

Polymer residue

Figure 16.35



© 2001 by Prentice Hall

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Chapter 16 Review


Quality Measures

469


Troubleshooting

440


Summary

471


Key Terms

472


Review Questions

472


Equipment Suppliers’ Web Sites

473


References

474