Heirarchical Layout using Layout XL

worshiprelaxedΗλεκτρονική - Συσκευές

2 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

96 εμφανίσεις

C:
\
Program Fi les
\
neevia.com
\
docConverterPro
\
tem
p
\
NVDC
\
6102047D
-
7DBF
-
4D5F
-
AE74
-
1CAA879E0874
\
worshiprelaxed_ee8df77f
-
5d02
-
409d
-
b691
-
bfdd77f6d844.docx


bolson
@csupomona.edu

11/2/2013


Page
1

of
4


Heirarchical

Layout
using Layout XL


This tutorial assumes that you have completed a basic layout tutorial

Below is the schematic that we will be creating a layout for.




C:
\
Program Fi les
\
neevia.com
\
docConverterPro
\
tem
p
\
NVDC
\
6102047D
-
7DBF
-
4D5F
-
AE74
-
1CAA879E0874
\
worshiprelaxed_ee8df77f
-
5d02
-
409d
-
b691
-
bfdd77f6d844.docx


bolson
@csupomona.edu

11/2/2013


Page
2

of
4


1)

In the top toolbar select:

Tools
-
>
Design Synthesi s
-
>Layout XL

2)

In the new
window s
elect
creat
e

new

3)

Select
OK

to close the window

4)

Select
OK

to close the new window

5)

You will see a Virtuoso layout window

6)

In the top tool
bar of the new Virtuoso layout window select
Design
-
> Gen from Source

7)

Select
all the pins and change their widths
to be .9um and the layer to be metal 1

8)

Select update to change the properti es of the pin


9)

Under
Pin label options
select
roman

as the font (it is easier to read)

10)

Select
OK
at the top to close the window

11)

In top toolbar of the layout Virtuoso window select
O
ptions
-
>Di splay

12)

Change the Display levels to
stop at
10

13)

Select

OK
to close the window

14)

In the Virtuoso Layout window you will see
NOR2 gates that you created and the pins. Put them in
the PrBound box

15)

To save area make sure to merge the
n
-
wells

16)

Place the
ins appropri at ely on the layout


17)

the transistors and pins.
T
hey all must go in the PrBound Box (the purple box)


18)

Move the transistors
(bindkey m)
into the Pr Bound box

as shown below
.
You will have to
merge sources
and drains by overlapping transistors.

As you do this notice that lines appear indicating the connectivity
of
the gate, source and drain of the transistor
s

to the corresponding pins

pi ns

C:
\
Program Fi les
\
neevia.com
\
docConverterPro
\
tem
p
\
NVDC
\
6102047D
-
7DBF
-
4D5F
-
AE74
-
1CAA879E0874
\
worshiprelaxed_ee8df77f
-
5d02
-
409d
-
b691
-
bfdd77f6d844.docx


bolson
@csupomona.edu

11/2/2013


Page
3

of
4


19)

Move the pins to correspond with the layout (as shown below
). When you move the pins you are moving
text and a box (
The box
not visible until selected). Make sure that you select both.

o

You may remember that the pins were originally assigned layers ex) A was assigned to ploy and
Y to metal 1. When the pins are p
laced on the layout they should be placed on those layers. If
not, change the pin layer by selecting

the box
that the pin is affiliated with and selecting bindkey q
to change the properties

so that the layers agree

20)

If you look at the virtuoso schematic w
indow you will notice that when a transistor or pin is selected on the
layout then it is highlighted on the schematic.




C:
\
Program Fi les
\
neevia.com
\
docConverterPro
\
tem
p
\
NVDC
\
6102047D
-
7DBF
-
4D5F
-
AE74
-
1CAA879E0874
\
worshiprelaxed_ee8df77f
-
5d02
-
409d
-
b691
-
bfdd77f6d844.docx


bolson
@csupomona.edu

11/2/2013


Page
4

of
4



21)

Complete the layout of the nor2 as shown