ASIC Design using Organic Transistors

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2 Νοε 2013 (πριν από 3 χρόνια και 9 μήνες)

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1


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----------------------------


INDIAN INSTITUTE OF TECHNOLOGY BOMBAY


Department of Electrical Engineering


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SYNOPSIS


o
f the Ph.D. thesis entitled


ASIC Design using Organic Transistors


Proposed to be submitted in


P
artial fulfillment of the requirements

f
or

the degree of


DOCTOR OF
PHILOSOPHY


of the


INDIAN INSTITUTE OF TECHNOLOGY BOMBAY


by


Ramesh Raju Navan


Supervisor
:

Prof. V. Ramgopal Rao


Co
-
Supervisor
:

Prof.
M. Shojaei Baghini



----------------------------------------------------------------

2


The field of low
-
cost organic electronics is a relatively active topic of research in the
domain of semiconductor technology. Activities started in the 1980s
with

demonstrati
o
n

of

organic field effect transistors (OFETs) which ma
d
e use of special organic c
ompounds for the

semiconducting channel instead of crystalline silicon
.
First successful

f
ield eff
ect transistor
using conducting polymers was demonstrated by

Koezuka and coworkers [1
]. They
demonstrated that it is possible to control

the current
fl
owing b
etween source and drain
through gate
. These OFETs cannot compete with silicon
-
based transistors regarding
switching speed or packing density but provide prospects of considerably reduc
ed

fabrication
costs, large
-
area manufacturing or implementing mechanically flexible integrated circuits

[2]
.
These advantages generate applications of OFETs where fabrication costs or flexibility
is

more important than e.g. switching speed of the transistor
s

[3]
. One example is the
implementation of extremely low
-
cost radio
-
frequency identification (RFID) tags

[
4
]
.


Currently, low
-
cost organic electronics is in the
active

stage of development and
optimization of devices and processes. Various materials and
fabrication processes are
continuously tested and optimized

for improved performance
.
There is a need of
phtopatternable high
-
k gate dielectric

for large area and low processing cost applications.
Circuit simulation is an important part in this process as
it provides insight into the
performance potential of existing OFET generations in OFET based circuits. In the course of
circuit simulation, devices are modeled and the electrical performance of typical application

circuits is analyzed. Employing circuit s
imulation in the process of optimizing device
performance
consists of numerous
matching device characteristics,

simulating application
circuits and extracting performance figures from simulation results. Therefore, efficient
methods of
simulating

OFET devi
ces and analyzing OFET
-
based circuits by use of circuit
simulation are needed in order to automate the analysis process as much as possible.


Objective of th
is work

is
to enhance

mobility
, tun
e

the threshold

voltage
, gate
dielectric optimization

and
develop

a novel device and circuit simulation technique
. To
overcome some of the shortcomings of O
FET

circuits we have
also shown

circuit
design

approaches
for
O
F
E
Ts.
In this work we have mainly studied
solution

processed poly (3
-
hexylthiophene) (P3HT) and

vacuum evaporated pentacene

based p
-
type
OFET
s
.

Several
methods of dielectric surface improvement were found favorable for organic layer and they
were compared with each other. A novel procedure for

octadecyltrichlorosilane

(OTS)
deposition was explored and verified experimentally to give i
mproved mobility of pentacene
3


O
F
E
Ts.

The top
-
cont
act bottom
-
gate configurations are

shown in figure 1 below
were used to
see the effect of SAM on OFETs.



Figure
1

Top
-
contact bottom
-
gate
OFET

structure with and without SAM.



The surface
characterization
methods
carried out

were contact angle measurement and
atomic force microscope

(AFM)

study.

Contact angle values and average RMS roughness of
the surface after treatment
are

tabulated in table 1. The
OTS deposition on silicon dioxide and
hafnium oxide w
ere

found to give the highe
r

mobilities
compared to other methods tried
.
The
mobility values are listed in table 2.



Table 1

Contact angle values

and RMS roughness
after


different surface treatments on SiO
2

samples.









Surface Treatment on
SiO
2

Contact Angle

RMS roughness

(nm)

Bare SiO
2

~ 41°

0.56

OTS

~ 68°

0.83

HMDS

~ 84°

1.32

Piranha + OTS

~ 95°

1.98

4


T
able 2

Mobility comparison after different surface treatment
s
.











We have report
ed the mobility enhancement of
P3HT

based

p
-
type of organic
transistors by dispersing ZnO (zinc oxide) nanostructures into it. A facile, low
-
cost, one
-
step,
aqueous
-
based chemical approach has been demonstrated for the fabrication of ZnO
nanorods. OFETs based on this nanocomposite show a mobility

enhancement of more than
60%. However, there is still scope for further improvement in terms of better dispersion of
ZnO nanostructures and the possibility of obtaining higher
mobilities
.





Figure 2

(a) Cross
-
sectional view of the P3HT/ZnO
nanocomposite based bottom contact
organic fie
l
d effect transistor

(b)
t
ransfer (
I
DS
-
V
GS
) characteristics comparison for

different concentration
s

of ZnO nanorods in P3HT/ZnO nanocomposite

where V
GS

is varied from +10 to
-
40 V & V
DS

=
-
40 V
.




Substrate

Mobility (cm
2
/Vs)

Bare

SiO
2

0.092

Piranha + OTS

0.138

HMDS

0.193

OTS

0.265

5


The
threshold voltage is a very important parameter o
f

a transistor. Many circuits
require a tuning in its value without changing the materials. While in MOSFETs, precise
formulae exist to determine threshold voltage exactly and can also be changed by doping,
substrate bias
etc., this is not
so easily
possible in O
F
E
Ts.
In this work
,

w
e
were able to

tune
the threshold voltage of the organic transistor by using the
self
-
assembled monolayer

(
SAM
)

of metallated porphyrin. The principle involved behind this approac
h is the use of dipole
moment of the porphyrin molecule. The dipole moment introduces an electric field in its
vicinity and hence an extra voltage needs to be applied to compensate this field and then form
the channel. This phenomenon changes the threshold

voltage of the transistor.
The formation
of SAM was confir
med by the UV
-
Vis spectroscopy.

The transfer characteristics log |I
DS
|
versus V
GS

curves obtained for these devices
with different
porphyrin
SAM
are shown in
figure 3
. Here we took
silicon di
oxide
of

100 nm thickness
and device dimensions

of
W =
4186 µm and L = 100 µm values.
We
have
observed
that
a
long with the threshold voltage the

mobility, off
-
current and leakage
is also getting

affected by the SAM layer. An approach to
solve these issues was tr
ied by incorporating SAM in between gate and dielectric instead of
dielectric and semiconductor. The results obtained seem to solve the aforementioned issues
and is a new direction of research for achieving the tuning.



Figure 3

L
og |I
DS
|
-
V
GS

curve for OFET with W = 4186 μm and L = 100 μm
for oxide thickness of 100 nm.


The gate dielectric
also
plays a very important role in organic transistor performance.
There are many solution processed

g
ate dielectrics available but these materials need to be
thick enough to avoid pin
-
holes, consequently require a high device operating voltages and
these materials also have a lower dielectric constant. Metal oxides have a higher dielectric
6


constant, but t
heir deposition process is rather expensive and not easily adaptable for large
area manufacturing. Here we have demonstrated organic field effect transistors (OFETs) with
photo
-
patternable, solution processed nanoparticle composite high
-
k gate dielectric l
ayer. The
dielectric layer consists of Barium Titanate (BT) nanoparticles dispersed in SU
-
8, which
makes it possible to use solution
-
processable methods to prepare the dielectric layer. The
dielectric constant k of the nanoparticle composite films
are

tune
d over a wide range by
varying the concentration of BT particles, which enables lower voltage operation possible
with these composite gate dielectric films.

The gate dielectric optimization results are shown
in figure 4.

OFETs with P3HT as the semiconducti
ng layer have been demonstrated; it was
found that the OFETs with the nanocomposite dielectric layer show a significant
improvement in the drive current yet retaining the photopatternability, which is an advantage
for circuit fabrication. The composite bei
ng a high
-
k enables low voltage operation (

4

V)
compared to pristine SU
-
8 as a gate dielectric operating at high voltages (

40

V). Working
organic transistors and inverters with a high
-
k nanocomposite dielectric layer (k

>

13) with
considerably lower leak
age current have been demonstrated. This method allows low cost
preparation of OFETs without the complicated gate dielectric deposition methods.


(a)



(b) (c)


Figure 4

(a)
Effect of BT wt% on the thickness of

the spin coated composite film. (Inset
shows the structure of the MOS capacitor)

(b)
Capacitance

v
s.

frequency plots for different
concentration of BT nanoparticles blended into the SU
-
8 dielectric films and

(
c
)
d
ependence of resistivity and dielectric constant on BT wt%.



The
O
F
E
T
device structure is shown in
f
igure 5(a). For comparison purposes, we
have also fabricated OFETs using pristine SU
-
8 as gate dielectric of 500 nm thickness. The
nanocomposite

of
SU
-
8 with 0.88 BT wt% of high
-
k ≈ 13.1 was characterized
.

H
igher
concentration of BT increases the

gate leak
age, which is undesirable. The OFET
7


characteristics using P3HT as the semiconductor (
D
imensions W/L = 24,000 µm/50 µm) with
the pristine SU
-
8 and SU
-
8/BT nanocomposite gate dielectrics have been shown in
f
igure
5(b, c) and 5(d, e)
respectively.



Figure
5

(a) Schematic cross
-
section of bottom contact organic fie
l
d effect transistor with a
nanocomposite gate dielectric (b) & (c)
t
ransfer (
I
DS
-
V
GS
)

&
o
utput (I
DS
-
V
DS
)

characteristics

of pristine SU
-
8 gate dielectric, and (d) &

(e)
t
ransfer

&
o
utput characteristics of composite

SU
-
8 with 0.88 BT wt% gate dielectric

(W/L = 24000 µm/50 µm).



Figure
6
(a) shows the realization of organic inverters with proper interconnections
following the lithographic steps. Figure
6
(b) shows the schematic of an organic inverter with
enhancement mode driver (M1) and load (M2). Figure
6
(c) shows the DC transfer
characteristics of the fabricated organic inverter with input voltage varied from 0 to 4 V and
the bias voltage V
DD

kept at 4
V. The inverter shows an excellent switching behavior with a
DC gain (Av) of
-
1.76 and output voltage swing of 2 V.



8



Figure
6

(a) Cross
-
sectional structure of the organic inverter after semiconductor layer
formation (b) Schematic of all p
-
type organic
inverter with enhancement mode driver (M1)

and l
oad (M2) and (c) DC transfer characteristics of a typical organic inverter.



The

transport phenomenon in organic semiconductors is still not fully
understood and
no univocal physical models exist for
organic

device simulation.

In this context w
e w
ill
discuss
device and circuit
simulation
approaches for OTFTs, as these devices are difficult to
simulate using a standard simulator.

One approach of c
ircuit simulation of O
F
E
Ts was to
extract equivalent
SPICE (Simu
lation Program with Integrated Circuit Emphasis)
parameters
of O
F
E
Ts with the help of particle swarm optimization (PSO) algorithm. The extracted
equivalent SPICE parameters are used as a device model for SPICE based circuit simu
lations.
Another approach fo
r O
F
E
T device simulation was done by use of ISE
-
TCAD (
I
ntegrated
Systems Engineering
-

Technology Computer
Aided Design
) in it the device parameters for
silicon were replaced by those of organic semiconductor. The results obtained from device
simulation pr
ocedure were

then used to generate the Look
-
up Tables (LUTs) of th
e organic
devices. LUT of the O
F
E
T can also be directly obtained from the experimental data. LUT
9


generated is used as a model file in SEQUEL (
Solver for circuit EQuations with User
-
defined
E
L
ements)

for simulating circuits.
Figure
7

shows the measured vs. simulated output
characteristics of a
fabricated

device
with SiO
2

of 45 nm thick and W/L = 2000 μm/100 μm
.

An acceptable match was observed in simulated and measured characteristics of the
devices
by tuning the device parameters.


Figure
7

Measured vs.
s
imulated I
DS
-
V
DS
characteristics for
OFET
s fabricated

(Data scaled to width W=1 μm).


A
n enhancement mode inverter is simulated for DC and transient analysis using
SEQUEL and SPICE. The circuit is shown in figure
8
(a) inset. T
he results are shown in
figures
8(a) and
8
(b). It is observed that both LUT based and equivalent parameter extraction

approaches give comparable results. To get higher DC gain in transfer characteristics,
driver
M1

(= 5000
μm
/150
μm
)

needs to have higher W/L ratio compared to M2

(= 1000
μm
/150
μm
)
.

Simulated results were verified experimentally.


(a)



(b)

Figure
8

(a) DC transfer characteristics and (b)
t
ransient response of the simulated


all p
-
type enhancement mode organic inverter for V
DD

= 5

V
.



10


With the availability of only p
-
type
OFET
s being more reliable and stable, we need to
look into only

p
-
type transistor based circuit design styles. Inverters with only p
-
type device,
is in general inferior to complementary style in terms of robustness and power consumption.
The noise margins of the circuit decreases making it less robust. Therefore, boot
strap circuit
design style was thus proposed to improve the output voltage swing considerably.


A new compact
OFET
-
based analog to digital converter (ADC) using only p
-
type
transistors was designed and simulated using LUT based approach in SEQUEL circuit
s
imulator. The LUT data was obtained from fabricated P3HT
-
based
OFET
s with the
developed high
-
k
nanocomposite
photopatternable gate dielectric layer.
The device structure
is shown in figure
9
(a). The measured
OFET

output characteristics is compared with the

LUT
based simulation results (
d
imensions W/L = 24,000 µm/50 µm) as shown in figure
9
(b)
.







(a)


(b)

Figure
9

(a) Device structure (b)
m
easured vs. LUT simulated output

characteristics for
OFET
s.



LUT
-
based
device

simulation shows a good match. LUT approach can be made more
robust against device variations within the same batch/sample and between the samples of
different batches by taking the mean value of the device characteristics and then generating
LUT of the d
evice
,

thereby compensate phenomenon such as bias stress effects and stability
effects

which is critical for organic devices.

T
he fabricated
OFET

device is represented using
look
-
up tables in
a general purpose
circuit simulator SEQUEL.
Further test circuit
s were
designed and fabricated using all p
-
type organic transistors. As an example, transient
11


performance of an inverter using enhancement
-
mode p
-
type transistors

is simulated using
SEQUEL and compared with the experimental results
. The inverter circuit is

shown in figure
10
(a). As shown in figure
10
(b), LUT
-
based simulation is compared with the experimental
results validating the simulations.



(a)


(b)

Figure
10

(a)
OFET

i
nverter using only p
-
type transistors and (b)
t
ransient response
of the simulated p
-
type enhancement
-
mode organic inverter for V
DD

= 4 V
.


Compact organic
transistor
ADC, which has a wide range of applications like signal
conditioning of signals from organic sensors, is designed using only p
-
type
OFET
s. From
design point of view, circuit modules with fewer transistors are preferred due to yield and
stability of P3HT
-
ba
sed components.

First, a technique for controlling the switching
threshold of inverter using an external control voltage (Vc) is proposed
.
This switching
-
controlled inverter, having four transistors, is the main block of the proposed compact ADC.
The
diffe
rential
inverter circuit is shown in figure
11
(a). Using a symmetrical layout
differential architecture of the inverter makes it less sensitive to variation of threshold voltage
of input transistors M1 and M3. It should be noted that variation window of th
reshold voltage
in organic transistors is higher compared to Si transistors. Transistor (Mcs) provides bias
current of the differential inverter.

V
DD

value was limited to 5 V to avoid breakdown and high
leakage of the organic transistors. The results are s
hown graphically in figure
11
(b).


A circuit for a simple analog to digital converter (ADC) with four q
uantization levels
is suggested
. This circuit is merely an extension of the differential inverter circuit. The
schematic of the circuit is shown in figure
12
. In the circuit shown in figure
12
, the voltage
divider generates three different voltage levels, each of which serves as a contr
ol voltage for a
12


differential inverter (figure
13
(a)).

The

inverter is used after every output voltage to produce
a uniform high output voltage level, as shown in figure
13
(
b
).

The proposed design and
circuit simulation
results show a great promise for sim
ulation and complex designing
approach advantageous for different organic electronic applications.



(a)


(b)

Figure
11

(a) Differential inverter circuit using four p
-
type transistors. (b) LUT
-
based
simulation results of the switching characteristic of the inverter for higher values

of V
IN
, the

output voltage tends to saturate to the threshold voltage of
M2.




Figure 12

Block diagram of the ADC circuit synthesized using the voltage divider

and the differential inverter circuit.


13





(a)




(b)


Figure 13

(a) Cascade circuit of a differential and simple inverter for each single bit of ADC

(b)
simulation

results of the ADC.


Reference
s


1.
A. Tsumara, H. Koezuka

and T. Ando, “
Macromolecular electronic

device: Field
-
eff
ect
transistor with a polythiophene

thin
film,”
Appl. Phys. Lett.
, Vol.
49
, no.
18
, pp.
1210
-
1212,

Nov
.

1986.


2.
C. D. Dimitrakopoulos and P. R.L. Malenfant, “Organic thin film transistors for large area
electronics,”
Adv
. Mat
er
.
, Vol. 14, no. 2, pp. 99
-
117, Jan. 2002.


3.
S. R. Forrest, “The path to Ubiquitos and low cost organic electronic appliances on
plastic,”
Nature
, Vol. 428, no. 6986, pp. 911
-
918, Apr. 2004.


4.
R. Rotzoll, S. Mohapatra, V. Olariu, R. Wenz, M. Grigas, K. Dimmlerb, O. Shchekin and
A. Dodabalapur, “Rad
io frequency rectifiers based on organic thin
-
film transistors,”
Appl.
Phy. Lett
.
,
V
ol.

88, no. 12, pp. 123502
-
(1
-
3), Mar. 2006.


Publications based on the thesis


Peer
reviewed international journals
:


1.
Ramesh R. Navan
, K. Prashanthi, M. Shojaei
Baghini and V. Ramgopal Rao, “
Solution
processed photopatternable high
-
k nanocomposite gate dielectric for low voltage organic
field effect transistors
,”
Microelectron
.

Eng
.
, Vol. 96, pp. 92
-
95, Aug. 2012.


2.


Ramesh R. Navan
,
B. Panigrahy
,
M. S. Baghini
,
D. Bahadur

and
V. R. Rao
, “
Mobility
enhancement of sol
ution
-
processed poly(3
-
Hexylthiophene) based organic transistor
using zinc oxide nanostructures,

Composites Part B
,
Vol. 43, no. 3
, pp. 1645

1648, Apr.
2012.

14



3.


Ramesh R. Navan,
K. Prashanthi, Anukool Rajoriya, M. Shojaei Baghini, V. R. Palkar
,
V. Ramgopal Rao, “A Novel High
-
K (K > 40) Gate Dielectric for pentacene Organic
Thin Film Transistors,”
World Journal of Eng
.
, Vol. 6, pp. 731
-
732, 2009.


4.

Anshuman Kumar,
Ramesh R. Navan
, Ajay Kushwaha, M. Aslam and V. Ramgopal
Rao, “Performance Enh
ancement of p
-
type Organic Thin Film Transistors using Zinc
Oxide Nanostructures,”
Int. J. Nanosci.
,
Vol. 10
,
no. 4
-
5, pp. 761
-
764, Aug. & Oct. 2011.


5. H. N. Raval, S. P. Tiwari,
R. R. Navan
, S. G. Mhaisalkar and V. R. Rao, "Solution
Processed Bootstrapped Organic Inverters based on P3HT with a High
-
K Gate dielectric
Material,"
IEEE Electron Device Lett.
, Vol. 30, no. 5, pp. 484
-
486, May 2009.


International conferences:


1.

Ramesh R.

Navan
, Bharati Panigrahy, M. Shojaei Baghini,D. Bahadur and V. Ramgopal
Rao "Mobility Dependence of Solution
-
Processed Poly (3
-
hexylthiophene) Based
Organic Transistor on Aspect Ratio of Zinc Oxide Nanostructures,"
XVI
th

International
Workshop on the Physics of Semiconductor Devices
(IWPSD
-
2011), Kanpur, India, 19
-
22
Dec. 2011.


2.

Anshuman Kumar,

Ramesh R. Navan
, A. Kushwaha, M. Aslam, V. Ramgopal Rao
,
"Performance Enhancement of p
-
type Organic Thin Film Transistors using Zinc Oxide
Nanostructures,"
International Conference on Nano Science and Technology

(ICONSAT
-
2010), Mumbai, India, 17
-
20 Feb. 2010.



3.

Rohit V. Pandharipande,
Ramesh R. Navan
, Urmimal
a Roy, Mrunal K.Khaderbad, M.
Yedukondalu, M. Ravikanth, V.Ramgopal Rao, "Threshold Voltage tuning of Pentacene
OFETs using Self Assembled Monolayer of Metallated Porphyrin,"
International
Conference on Nano Science and Technology

(ICONSAT
-
2010), Mumbai, I
ndia, 17
-
20
Feb. 2010.


4.

Ramesh R. Navan
, H. N. Raval, M. S. Baghini and V. R. Rao, "Low Voltage Patterned
Gate Pentacene Organic Circuits with Hafnium oxide High
-
K Gate Dielectric,"
Proceedings of the 7th Organic Semiconductor Conference

(OSC
-
09), London,
UK, 28
-
30 Sept. 2009.


5.

Ramesh R. Navan,
K. Prashanthi, Anukool Rajoriya, M. Shojaei Baghini, V. R. Palkar,
V. Ramgopal Rao, “A Novel High
-
K (K > 40) Gate Dielectric for pentacene Organic
Thin Film Transistors
,


The 17
th

International Conference on COMPOSITES/NANO
ENGINEERING
(ICCE
-

17), Hawaii, USA, 26
-
31 Jul. 2009.


6.

R. R. Navan
, R. A. Thakker, S. P. Tiwari, M. S. Baghini, M. B. Patil, S. G. Mhaisalkar
and V. R. Rao, "DC & Transient Circuit Simulation Methodologies for O
rganic
Electronics
,
"
Proceedings of the IEEE International Workshop on Electron Devices &
Semiconductor Technology

(IEDST
-
2009), Mumbai, India, 1
-
2 Jun. 2009.