A Study of Si-Nanowire Transistor in Working Temperature Range

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VSRD
-
IJEECE, Vol. 2 (8
), 2012
,
1
-
5


____________________________

1
,2
Research Scholar
,

2
Assistant Professor
,

1,2,3
Department of
Electronics &
Communication
Engineering
,

Swami
Vivekanand

Subharti University, Meerut
,
Uttar Pradesh,
INDIA.
*Correspondence :
p
rashantdixit.pd@gmail.com

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A Study of Si
-
Nanowire Transistor in

Working Temperature Range

1
Prashant Dixit
*
,
2
Mohini Preetam Singh

and
3
Vivek Gupta

ABSTRACT

This paper represents the temperature

effect on silicon nanowire transistor. Current
-
voltage characteristics with
practical values of temperature (
-
23
0
C

to +62
0
C) are simulated. Variation of drain current, ON current to OFF
current ratio (I
on
/I
off
) and threshold voltage at above temperatures
are investigated. We observed that first in
linear region there is an increasing trend in current with increasing temperature, while in saturation region there
is decreasing pattern in drain current with increasing temperature
.

Keywords :
Nanowire Transist
or, Threshold
Voltage
, Temperature.

1.

INTRODUCTION

The silicon nanowire transistor (Si
-
NWT) has attracted broad attention from both the semiconductor industry
and academic fields [1]
-
[3]. Silicon nanowires are attractive option for many nano
-
electronic applications.
Nanowires are nanoscale structures which

are frequently single crystal materials and are typically cylindrical in
shape. They can be formed in a variety of materials including metals and insulators, but are most frequently
fabricated using semiconducting materials. Since semiconductors are used
in transistors, semiconducting
nanowires are of the most interest. They have attracted attention not only because of their extremely small size,
but because their size causes new physics (quantum effects) to apply, which do not occur classically, that can
cause changes in material properties [4]. Further the temperature can also change the band gap of
semiconductors so it is practical to study the temperature behaviour of Si nanowire transitors. The operation of
future electronic devices, and a wide array o
f additional applications, will depend on the properties of these
nanowires. A new generation of ultra small transistors and more powerful computer chips using tiny structures
called semiconducting nanowires will be more applicable in the future after more

discoveries by researchers.
The fabrication of nanowire FETs is still a technology under development that requires further innovations
before challenging state
-
of
-
the
-
art MOSFETs. To understand device physics in depth and to assess the
Prashant Dixit

et al

/ VSRD
International Journal of Electrical, Electronics

& Comm. Engg. Vol. 2 (8
), 2012

Page
2

of
7

performance limits
of SNWTs, simulation is becoming increasingly important. Simulation tools can support the
experimental work to accelerate the development of NW FETs. The temperature dependence of the drive current
in Si
-

nanowire Field
-
Effect Transistors is very important

part of this paper.



Fig.
1 :

SNWT
Structur
e

2.

SIMULATION

The simulation tool we used here for investigation of the effects of temperature on nanowire
transistors
. This
simulation tool is for nano
-
scale
s
u
rrou
nding

-

gate FET structure.
The simulation tool based on PROPHET or
PADRE simulators and both are developed in Bell Laboratories. PROPHET is a partial differential equation
solver for 1, 2, or 3 dimensions and PADRE is a device
-
oriented simulator for 2D or 3D device with arbitrary
ge
ometry [12]. It provides many useful plots for engineers and deep understanding of physics. The simulation
tool provides self
-
consistent solutions to the Poisson and drift
-
diffusion equation [11]. The simulation tool is
used to simulate ballistic transport

in the calculation of the characteristics for SiNWT [12]. At room
temperature, the devices have high normalized ON
-
current (I
ds

at V
ds

= V
gs

= 1.2 V) of 0.68 mA/µm
(normalized to wire thickness of 7 nm), Vth =

0.2
V, with Ion/Ioff >



and low gate lea
kage of

2

5 pA at
room temperature. When the temperature is reduced, the measured Ids
-

Vgs characteristics with Vds = 50 mV
at different temperatures in both linear and log scales to delineate the subthreshold and strong inversion regions.
Similar to th
e low
-
temperature effect in bulk devices in the subthreshold region , Ids reduces as temperature
decreases on account of increase in Vth. However, even in the strong inversion, the current remains lower at
lower temperatures than that at higher temperature
, as can be seen from the linear scale. This is contrary to the
intuitive expectation, since the increase in mobility (

ph) from reduced phonon scattering would be expected to
enhance the current at lower temperatures.

3.

RESULT

& DISCUSSION

At the first, the

characteristics of silicon nanowires transistor were simulated at different values of temperature
(250, 275, 300, 315, and 335

k) with following parameters: channel concentration (intrinsic) =






,
source length = drain length = 10nm, source and drain concentration (n
-
type) =





, channel length =
10nm, channel diameter = 6nm and oxide thickness = 2nm. For gate leakage current and according to
calculation of Y. Taur at gate oxide 1nm thick a
nd gate voltage range (0
-
1 V) gate current density range is (1
-



A/


), which mean for our transistor gate area (942


) leakage current will be 9.42pA at Vg = 1V and
this is very small and has no effect on drain current as in “Fig. 2. It can be not
ed that current (normalized to
diameter) increases with increasing temperature at low Vg (>0.4V) and decreasing at high Vg (<0.4V). Also it
can be noted that changing in working temperature tends to change in ON current to OFF current ratio (I on/I
Prashant Dixit

et al

/ VSRD
International Journal of Electrical, Electronics

& Comm. Engg. Vol. 2 (8
), 2012

Page
3

of
7

off), t
hreshold voltage (VT). VT decrease with increasing temperature and temperature effects parameter
(

Id/

T) increase with increasing gate voltage and the greatest effect done at Vg = 1V. Therefore, gate and
drain electrodes must connect directly to Vdd = 1 a
nd source electrode connects to be ground (as shown in “fig.
4”) to get the best used of a transistor as a transistor as a temperature sensor.

“fig. 3” illustrate the effect of temperature on (I on/I off). Value of (I on/I off) ratio decrease exponentiall
y with
increasing temperature, it can be noted that at 275

k greater Ion with smaller Ioff and this tend to best (I on/I
off) ratio. to get the best sensitivity of current with temperature gate and drain electrode connects to be ground
(shown in “fig. 4”)
to get greater (

Id/

T) to use a transistor as a temperature sensors.


Fig.

2

:

Variation
Current With Working

Temperature
if Vd=1V In Current Above


Fig.

3

:

Variation of ON
Current
to OFF

Current
(Ion/Ioff)
With Working

Temperature When
Vd=1V
.

0.01
0.015
0.02
0.025
250
275
300
325
350
I
DS (A/um)

Temperature (K)

1.00E+05
2.10E+06
4.10E+06
6.10E+06
8.10E+06
1.01E+07
250
300
350
I
ON
/I
OFF

Temperature (K)

Prashant Dixit

et al

/ VSRD
International Journal of Electrical, Electronics

& Comm. Engg. Vol. 2 (8
), 2012

Page
4

of
7


F
ig.
4

:

Variation of T
hreshold Voltage (Vth)
With Working
Temperature When
Vd=1V
.

4.

CONCLUSION

Temperature
effects
of silicon nanowire transistor were simulated
using simulation tool.
Transfer characteristic
at Vd = 1V was investigated with different values
of working

temperature (250, 275, 300, 315
, and 3
35
k
).The
result
can be divided into two regions, at first region t
here is an increasing in (I on/I off) with increasing
with
increasing temperature, while the second region there is decreas
ing in the thresh
old voltage (Vth
) and (I on/I
off) ratio with increasing working temperature. Maximum sensitivity of current with temperature done at Vd =
Vg = 1V
.

5.

REF
E
RENCES

[1]

R.Huang et al., “Experimental Demonstration of Current Mirrors Based on Silicon Nanowire Transist
or for
Inversion and subthreshold Operations”, IEEE Trans. On Electron Devices, vol. 58, no
. 10, pp. 3639
-
3642,
Oct. 2011.

[2]

Martinez, M. Aldegunde, N. Seoane, A. R. Brown, J. R. Barker, A.

Asenov, “Quantum
-
Transport Study on
the Impact of Channel Length

and

Cross Sections on Variability Induced by Random Discrete Dopants

2011 IEEE Colloquium on Humanities, Science and Engineering Research (CHUSER 2011), Dec 5
-
6 2011,
Penang

[3]

N. Liao, C. Chen, and K. N. Tu, “Thermoelectric characterization of Si thin films in
silicon
-
on
-
insulator
wafer,” J. Appl. Phys., vol. 86, no. 86, pp. 3204

3208, Sep. 1999.

[4]

T. Kamins, “Beyond CMOS Electronics: Self
-
Assembled Nanostructures,”
The Electrochemical Scoiety
(ECS) Interface
, p. 46
-
49, Spring 2005.

[5]

Subhash C. Rustagi, N. Singh, Y
. F. Lim, G. Zhang, S. Wang, G. Q. Lo, N. Balasubramanian, and D.
-
L.
Kwong

Low
-
Temperature Transport

Characteristics and

Quantum
-
Confinement Effects in Gate
-
All
-
Around

Si
-
Nanowire N
-
MOSFET

IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 10, OCTOBER 2007

[6]

Yasir H
ashim, and
Othman Sidek


Collaborative Microelectronic Design Excellence Centre, University
Science Malaysia, 14300 Nibong Tebal, Penang, Malaysia
, 2011 IEEE coiiquium of humanities, science
and engineering research (CHUSER 2011), Dec. 5
-
6 2011, Penang.

[7]

M
. Y. Doghish and F. D. Ho, “A comprehensive analytical model for metal
-
insulator
-
semiconductor (MIS)
0.15
0.2
0.25
0.3
250
275
300
325
350
Threshold Voltage (V)

Temperature (K)

Prashant Dixit

et al

/ VSRD
International Journal of Electrical, Electronics

& Comm. Engg. Vol. 2 (8
), 2012

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5

of
7

devices,” IEEE Trans. Electron Devices, vol. 39, no. 12, pp. 2771

2780, Dec. 1992.

[8]

M. Bescond, K. Nehari, J.L. Autran, N. Cavassilas, D. Munteanu, M. Lanno
o, “3D quantum modeling and
simulation of multiple
-
gate nanowire MOSFETs,” IEDM Tech. Dig., p.617, 2004.

[9]

R. V. Martínez, J. Martínez and R. Garcia,” Silicon nanowire circuits fabricated by AFM oxidation
nanolithography”, Nanotechnolog vol. 21, no. 24, 2009
.

[10]

J. Wang, E. Polizzi, M. S. Lundstrom, “A three
-
dimensional quantum simulation of silicon nanowire
transistors with the effective
-
mass approximation”, J. Appl. Phys., vol. 96, p.2192, 2004.

[11]

S. G. Kim; Gerhard Klimeck; Sriraman Damodaran; Benjamin P Haley
(2011), "MuGFET," DOI:
10254/nanohub
-
r3843.5. (DOI: 10254/nanohub
-
r3843.5).

[12]

http://nanohub.org/resources/NANOFINFET

[13]

Y. Taur, “CMOS design near the limit of scaling,” IBM J. Res. Develop., pp. 213

222, Mar./May 2002.

[14]

Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, “High performance silicon nanowire field
effect transistors,”
Nano Lett.
, vol. 3, no. 2, pp. 149

152, 2003.

[15]

N
. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar,

G. Q. Lo, N.
Balasubramanian, and D.
-
L. Kwong, “High
-
performance fully depleted silicon nanowire (diameter


5 nm)
gate
-
all
-
around CMOS devices,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 383

386, May 2006.

[16]

T.

I. Kamins, R. S. Williams, Y. Chen, Y.
L. Chang, and Y. A. Chang, “Chemical vapor deposition of
Sinanowires nucleated by TiSi2 islands on Si,” Appl. Phys. Lett., vol. 76, no. 5, pp. 562

564, Jan. 2000.

[17]

D
. D. D. Ma, C. S. Lee, F. C. K. Au, S. Y. Tong, and S. T. Lee, “Small
-
diameter silicon nanow
ire
surfaces,” Science, vol. 299, no. 5614, pp. 1874

1877, Mar. 2003.

[18]

J.

P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K.
Schruefer, G. Knoblinger, and P. Patruno, “Low
-
temperature electron mobility in

trigate SOI MOSFETs,”
IEEE Electron Device Lett., vol. 27, no. 2, pp. 120

122, Feb. 2006.

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