A Configurable Architecture for

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E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
1

A Configurable Architecture for
High
-
Speed Communication
Systems

Visvanathan Subramanian, Joseph G Tront,
Charles W Bostian, Scott F Midkiff,


Center for Wireless Telecommunications,

Virginia Tech, Blacksburg, VA

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
2

Outline


Motivation


Prototype Network Overview


Gateway Architecture


Conclusion

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
3

Outline


Motivation


Prototype Network Overview


Gateway Architecture


Conclusion

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
4

Motivation


Design Challenges Wireless
Communication Systems


Need to address difficult and
interesting issues related to
access mechanisms, error
rates, transmission speed and
bandwidth.


Need to convert high level protocol descriptions rapidly into
hardware and software that implement the system


Develop a thorough verification process and minimize costly
redesigns within shrinking time to market windows


E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
5

Motivation (2)


Modern Design Approaches


System speed and complexity require breaking away
from traditional DSP or processor based architecture.


Must take advantage of new technology and resources


Must be flexible enough to adapt to late changes in
protocols or standards


Reuse IP to reduce design time and effort

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
6

Outline


Motivation


System Overview


Gateway Architecture


Conclusion

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
7

Emergency Response
Communications


A disaster area of several miles
with all communications wiped
out.


Landline connections exist at the
perimeter of disaster area


Solution: LMDS “fixed”
Broadband Wireless for Disaster
Recovery and Emergency
Response Networks


Support of Internet Access, Audio/Video Conferencing, GIS
Applications etc. for field response personnel can make a big
difference in rescue and emergency management operations !

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
8

Prototype Network

High Data Rate

Cable/Wireless Connection

LMDS

IEEE

802.11b

Hub

Remote GIS

and other services

10/100

Base T

Remote

Remote

“Virtual Ethernet”

Remote

LAN

Remote

LAN

Existing Network

Infrastructure

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V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
9

System Overview

Radio

Antenna

...

Host

Host

Antenna

Radio

Sounder

(Channel

Assessment)

Gateway

Router/

Switch

Radio

Monitor

Computer


GIS


Other applications

Wireless

Link

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V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
10

Gateway Salient Features


High Data Rates


Fast Ethernet 100 Mbps wire line interface


120 Mbps QPSK symbol mapped wireless radio
interface


Implements TDMA MAC scheme for deployment
of up to eight remotes


Implements adaptive FEC and ARQ scheme to
minimize end
-
to
-
end retransmissions


Uses Reed Solomon and Turbo Product Codecs for
multiple FEC coding levels


ARQ used based on channel/application requirements

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
11

Outline


Motivation


System Overview


Gateway Architecture


Conclusion

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
12

Architecture Design Space


ASIC vs. DSP vs. FPGA for Communication
Systems


Why FPGA ?


Excellent alternative to low efficiency of DSP based
designs and low flexibility of ASIC based designs


Availability of high performance FPGAs and
configurable IP Cores.


New FPGAs provide high density, embedded memory,
advanced routing, multiple I/O standard support

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
13

Configurable Architecture


Architecture consists of


Specialized Motorola PowerQuicc II


8255
Communication Processor


64
-

bit, 200MHz Power PC Core provides high performance,


32
-
bit 133 MHz Communication Processor simplifies network
interfaces : Built in Standards
-
based interfaces support for Fast
Ethernet, ATM , T1 / HDLC , UART


16 KB of Instruction and 16 KB of Data Cache


Xilinx Virtex
™ XCV
600 FPGA Co
-
processor


High Density : Up to 1M+ gates, 512 I/Os


High Performance : System frequencies up to 200MHz


Embedded Memory : Up to 16 KB of Internal Single/Dual Port
SRAM support

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V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
14

Configurable Architecture (2)


The data path elements consist of


“Functional Units” (FU) which modify or transform
data,


multiple scattered DMA
-
like “Processing Elements”
(PE) that move data


embedded and external “Memory Units” (MU) to store
data between stages.


Functional Unit1
Functional Unit 2
Memory
Element
Processing
Element 1
Processing
Element 2
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V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
15

Configurable Architecture (2)

Transmit Path

Receive Path

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
16


Gateway Prototype Architecture

60x Processor Address Bus (32)
Xilinx Virtex
FPGA
EEPROM
/Flash
Turbo Codec
Reed
Solomon
Codec
DUAL PORT
SRAM
Radio
Interface
Motorola
PowerQuicc II
Processor
10/100 Mbps
Ethernet PHY
RS 232
Transceiver
Media
Independe
nt Interface
(MII)
60x Processor Data Bus (64)
SDRAM
100 Mbps
Ethernet
Host
Interface
E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
17

Outline


Motivation


Prototype Network Overview


Gateway Architecture


Conclusion

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
18

Conclusion


TDMA MAC protocol was designed for
simultaneous operation of up to eight remotes.


Initial testing of concept was performed using
existing commercial point
-
to
-
point LMDS
modems.


The configurable architecture provides a highly
flexible architecture allowing for evolving or
changing standards and protocols.

E11

V Subramanian, JG Tront, CW Bostian, SF Midkiff

Slide
19

Conclusion (2)


The mapping of functional units was based on
performance tradeoffs as well as cost
considerations.


The

architecture

has

been

simulated

successfully

and

is

found

to

be

suitable

for

design

of

mid
-
range

systems

that

still

retain

a

high

level

of

complexity
.


Hardware

will

be

available

by

November

2002