New Router Architecture

wistfultitleΗλεκτρονική - Συσκευές

24 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

95 εμφανίσεις

Asaf SOMEKH, Oct 15
th
, 2013

Evolving Peering with a
New Router Architecture


Jean
-
David LEHMANN
-
CHARLEY

Compass
-
EOS

RIPE 67, Athens


j
d.lehmann@Compass
-
EOS.com



Asaf SOMEKH, Oct 15
th
, 2013

Peering Requirements / Challenges


Availability


Critical service on limited number of nodes


HA hardware features


Scalability


Bandwidth (100G interconnects)


Port density (Nx10G, 100G)


BGP scaling


FIB convergence


Dual stack IPv4/IPv6


MP
-
BGP to support both AFs


RIB/FIB scaling

Asaf SOMEKH, Oct 15
th
, 2013

Peering Requirements / Challenges


Stable/evolved BGP implementation


Flexible routing policy framework


4
-
byte ASN support, capability negotiation route reflectors,
confederations


Security


Infrastructure filtering


Accounting (
Netflow

v9, IPFIX)


Control plane protection


Colocation Cost control


Space


Power Consumption



Asaf SOMEKH, Oct 15
th
, 2013

Lessons from the Data Center Market

Virtualized Data Center

Clustering & Virtualization

Brought Efficiency to the Data Center

Monolithic Mainframes

4

Asaf SOMEKH, Oct 15
th
, 2013

Evolution of Industries

5

Data Centers

Networks

Can Networks Follow The Data Center Evolution?

Asaf SOMEKH, Oct 15
th
, 2013

So why do we have “Mainframe
-
like” routers?

6

It’s Electronics and Copper Limitations

Asaf SOMEKH, Oct 15
th
, 2013

Zooming in on the challenge


Chip I/O at speeds of
100
G is limited to a few centimeters


Requiring Amplification every
2
/
3
cm


Requiring MORE electronics


Requiring MORE cooling


Requiring MORE space


7

Asaf SOMEKH, Oct 15
th
, 2013

Compass
-
EOS
icPhotonics


World First Chip
-
to
-
Chip Optical Interconnect

8

Asaf SOMEKH, Oct 15
th
, 2013

i
cPhotonics™

World’s First Chip
-
to
-
Chip Optical Interconnect


1.34
Tb/s Full Duplex Bandwidth


Order of magnitude higher Chip
I/O Density.
64
Gb/a per mm
2


Passive optical links that stretch
to Hundreds of Meters vs.
Centimeters with Electronics


9


Direct Coupling to CMOS Chip


Low energy consumption:
10pJ/bit


Dozens of Patents Covering
Technology & Processes


Flexible form factor


Deployed in Production




Laser
Matrix

Photo
Detectors

Standard
I/O

Digital CMOS
chip

Direct optical
interface

Asaf SOMEKH, Oct 15
th
, 2013

Scale
-
Out

Enlarge VCSEL Matrix

12
x
14

Scaling icPhotonics™ to Even Higher Capacities

10


Scale
-
Up

Increase VCSEL
Speed

8
Gb/s

Per Channel


Today:
1.34
b/s

Over
10
Tb/s !

Asaf SOMEKH, Oct
15
th
,
2013

icPhotonics™


Inter
-
Chip Photonics

Revolutionizing Backplane Connectivity

The Traditional Way:

Multi
-
Layer
Midplane

and Switching Fabric

The Compass
-
EOS Way:

icPhotonics


Passive Optical Mesh

11

Complex

High Costs

High Power

Larger Systems

Limited BW/Slot

Simple

Lower Costs

Lower Power


Smaller Footprint

Unlimited BW/Slot

Asaf SOMEKH, Oct
15
th
,
2013

Enabling a simplified routing building
-
block

12

Asaf SOMEKH, Oct
15
th
,
2013

Enabling the Vision of Network Virtualization

Simplifying the Network
with

Routing Building Blocks
& SDN

13

Asaf SOMEKH, Oct 15
th
, 2013

How icPhotonics plays

14

Requirement

Solution

Colocation Cost Efficiency

Optical backplane

reduces the routers
physical foot print and power
consuptions

Efficient port density and
scale

Congestion free optical mesh enables
dense 100G solutions

Availability

Higher MTBF with passive

optical
backplane replaces active electronics
based fabric boards

Security

No “Security Vs. Capacity” Compromises


Full mesh based centralized policing

Enabled by Compass
-
EOS icPhotonics™

Asaf SOMEKH, Oct 15
th
, 2013

Asaf.Somekh@Compass
-
EOS.com