Transistors and Layout 1

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Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Topics


Basic fabrication steps


Transistor structures


Basic transistor behavior

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Fabrication services


Educational services:


U.S.: MOSIS


EC: EuroPractice


Taiwan: CIC


Japan: VDEC


Foundry = fabrication line for hire.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

l
-
based design


l

is the size of a minimum feature.


Specifying
l

particularizes the scalable
rules.


Parasitics are generally not specified in
l
units



In our 0.5 micron process,
l

= 0.25
microns.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Fabrication processes


IC built on silicon substrate:


some structures diffused into substrate;



other structures built on top of substrate.


Substrate regions are doped with n
-
type and
p
-
type impurities. (n+ = heavily doped)


Wires made of polycrystalline silicon
(poly), multiple layers of aluminum (metal).


Silicon dioxide (SiO
2
) is insulator.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Photolithography

Mask patterns are put on wafer using photo
-
sensitive material:

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Process steps

First place tubs to provide properly
-
doped
substrate for n
-
type, p
-
type transistors:

p
-
tub

p
-
tub

substrate

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Process steps, cont’d.

Pattern polysilicon before diffusion regions:

p
-
tub

p
-
tub

poly

poly

gate oxide

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Process steps, cont’d

Add diffusions, performing self
-
masking:

p
-
tub

p
-
tub

poly

poly

n+

n+

p+

p+

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Process steps, cont’d

Start adding metal layers:

p
-
tub

p
-
tub

poly

poly

n+

n+

p+

p+

metal 1

metal 1

vias

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Transistor structure

n
-
type transistor:

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Transistor layout

n
-
type (tubs may vary):

w

L

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Drain current characteristics

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

0.5

m transconductances

From a 0.5 micron process:


n
-
type:


k
n
’ = 73

A/V
2


V
tn

= 0.7 V


p
-
type:


k
p
’ = 21

A/V
2


V
tp

=
-
0.8 V

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Current through a transistor

Use 0.5

m parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.


V
gs

= 2V:

I
d

0.5k’(W/L)(V
gs
-
V
t
)
2
= 93

A


V
gs

= 5V:

I
d

= 1 mA

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Basic transistor parasitics


Gate to substrate, also gate to source/drain.


Source/drain capacitance, resistance.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Basic transistor parasitics, cont’d


Gate capacitance C
g
. Determined by active
area.


Source/drain overlap capacitances C
gs
, C
gd
.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.


C
gs

= C
ol

W


Gate/bulk overlap capacitance.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Latch
-
up


CMOS ICs have parastic silicon
-
controlled
rectifiers (SCRs).


When powered up, SCRs can turn on,
creating low
-
resistance path from power to
ground. Current can destroy chip.


Early CMOS problem. Can be solved with
proper circuit/layout structures.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Parasitic SCR

circuit

I
-
V behavior

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Parasitic SCR structure

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Solution to latch
-
up

Use tub ties to connect tub to power rail. Use
enough to create low
-
voltage connection.

Modern VLSI Design 2e: Chapter 2

Copyright


1998 Prentice Hall PTR

Tub tie layout

metal (V
DD
)

p
-
tub

p+