Nanowire Junctionless Transistors Nanowire Junctionless Transistors

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2 Νοε 2013 (πριν από 3 χρόνια και 10 μήνες)

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Nanowire
Nanowire
Junctionless
Junctionless
Transistors
Transistors
Jean-Pierre Colinge
Tyndall National Institute
University College Cork
1
www.tyndall.ieEvolution of the SOI MOSFET:
Better electrostatic control
“Gate-all-Around”
“Gate-all-Around”
“3 Gates”
“3 Gates”
“2 Gates”
“2 Gates”
Source
Gate
Drain
I
D
“1 Gate”
“1 Gate”
Buried oxide
Polysilicon Gate
Gate
Silicon
Source Drain
Fin
BOX
20 nm
Buried Oxide
Gate
Drain
Source
Buried oxide
Back gate (substrate)
2
www.tyndall.ie
Gate
GateSophisticated Silicon Nanowire Transistors ….
Source: CEA/LETI
3
www.tyndall.ieThe Trans-istor
http://www.yourdictionary.com/telecom/transistor
A contraction of trans-resistor, a transistor
is a solid-state active device that controls
current flow. A transistor comprises a
semiconducting material, such as silicon or
germanium, in three electrode regions
with two junctions.The regions are alternately
doped positive-negative-positive or negative-
positive-negative in a semiconducting sandwich,
so to speak.
4
www.tyndall.ie… 1925 ….
J. E. Lilienfeld:
"Method and
apparatus for
controlling electric
current" US patent
1745175 first filed
in Canada on 22nd
October 1925
J. E. Lilienfeld:
"Device for
controlling electric
current" US patent
1900018, filed on
28th March 1928
5
www.tyndall.ieD D D Dr r r ra a a ai i i in n n n
G G G Ga a a at t t te e e e
S S S S u u u ur r r rc c c ce e e e
o o o o
Trans-Resistor  Transistor
A A
+ +
P P P Po olly yS Sii G Ga at te e
S So ou ur rc ce e D Dr ra aiin n
+ +
N N S Siilliic co on n
B B
+ +
N N P Po olly yS Sii G Ga at te e
S So ou ur rc ce e D Dr ra aiin n
+ +
P P S Siilliic co on n
C C
A: 3D view of a junctionless transistor
B: cross section of an N-channel device
C: cross section of a P-channel device
6
www.tyndall.ieElectrostatic Pinchoff
The cross section must be small enough for channel region to be
depleted on carriers: Electrostatic Pinchoff
Source
Gate
Drain
t
si
W
si
7
www.tyndall.ieIncreasing Gate Voltage
Slightly above V
Below V
TH
TH
Higher V
Depletion gone
G
8
www.tyndall.ieElectrostatic Pinchoff: hydraulic analogy
9
www.tyndall.ieElectrostatic Pinchoff: hydraulic analogy
“ON” State: device is not pinched off
Gate
Source
Drain
10
www.tyndall.ieElectrostatic Pinchoff: hydraulic analogy
“OFF” State: device is pinched off
Gate
Source
Drain
11
www.tyndall.ieElectrostatic Pinchoff: hydraulic analogy
Subthreshold current: device is pinched a little bit
Gate
Source
Drain
12
www.tyndall.ieD D D Dr r r ra a a ai i i in n n n
G G G Ga a a at t t te e e e
S S S So o o ou u u ur r r rc c c ce e e e
Cross Section of Junctionless Transistor
13
www.tyndall.ieTEM
BOX
14
www.tyndall.ie
Polysilicon GateIncreasing Drain Voltage
V =200mV
D
V =50mV
D
V =600mV
D
V =400mV
D
15
www.tyndall.ieMeasured I (V ) of N- and P-channel
D D
junctionless transistors. L=1um, W=20nm

-7
-7
7.0x10
6.0x10
V =-1.4V V =-0.4~-1.4V
V =0.3~1.3V
g g
g
-7
V =1.3V
step=-0.2V
step=0.2V g 6.0x10
-7
5.0x10
-7
V =-1.2V
5.0x10
g
-7
4.0x10
V =1.1V
g
-7
4.0x10
-7
3.0x10 V =-1.0V
g
-7
3.0x10
V =0.9V
g
-7
2.0x10
-7
V =-0.8V
2.0x10
g
V =0.7V
g
-7
1.0x10
-7
1.0x10
V =-0.6V
V =0.5V
g
g
0.0
0.0
0.0 0.3 0.6 0.9 1.2 1.5
-1.5 -1.2 -0.9 -0.6 -0.3 0.0
Drain Voltage (V)
Drain Voltage (V)
Measured output characteristics of a
Measured output characteristics of an
P-channel device. W=20nm, L=1um,
N-channel device. W=20nm, L=1um,
W/L=0.02.
W/L=0.02.
16
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Drain Current (A)

Drain Current (A)
D
D
D
Measured I (V ) of N- and P-channel
D G
junctionless transistors. L=1um, W=20nm
-5
10
6
I /I ( V =1V)>10
ON OFF G
-7
10
5
I /I ( V =0.5V)>10
ON OFF G
-9
10
N-Type
P-Type
V =1.0V
V =-1.0V
-11
D
D
10
-13
10
W =30nm
mask
-15
10
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage (V)

17
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Drain current (A)
8
I /I ( V =2V)>10
ON OFF G

-5
10
V =1.0V
V =-1.0V
D
D
-7
10
V =0.05V
V =-0.05V
D
D
-9
10
-11
10
P-Type
N-Type
-13
10
W =30nm
mask
-15
10
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Gate Voltage (V)

18
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Drain current (A)
Temperature dependence

105
Gated resistor
Trigate FET
90
75
64 mV/dec
60
W =30nm, V =50mV
mask DS
45
200 250 300 350 400 450 500
Temperature (K)
Measured subthreshold slope vs. T in gated resistors and classical trigate
FETs. W=20nm, L=1um, W/L=0.02 .
19
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Subthreshold Slope (mV/dec)


Mobility Dominated by Impurity Scattering

400
W =30nm, V = 50mV
mask DS
350
Inversion-mode NMOS (undoped) (-36.2%)
300
250
Inversion-mode NMOS (doped)(-35.4%)
200
150
Junctionless PMOS (-16.5%)
100
50
Junctionless NMOS (-6.7%)
Accumulation-mode PMOS (-28.1%)
0
0 50 100 150 200
Temperature ( C)
20
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2
μ (cm /(Vs))
eff




















Leakage currents

-6
10
Junctionless FET, W =30nm
mask
V =-1.0V
DS
-8
10
-10
10

-5
10
T=30 C, 50 C, 70 C, 90 C,110 C,
-12
V =2.5V
Junctionless FET, W =30nm
10 DS
mask
130 C, 150 C, 170 C,190 C, 200 C
-7
10
-14
10
-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
-9
10
Gate Voltage (V)
-11
10
-13
10
T=30 C, 50 C, 70 C, 90 C,110 C,
130 C, 150 C, 170 C,190 C, 200 C
-15
10
-1.0 -0.5 0.0 0.5 1.0 1.5
Gate Voltage (V)
21
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Drain current (A)


Drain current (A)
Potential (V)
m
mm
m
Short-channel effects:
Junctionless vs. Inversion-mode device

Drain
Source Drain
Gate
22 1.6
V =1.0V, V =V
DS GS th
1.4
20
1.2
18 1.0
Inversion-mode
Junctionless
0.8
MuGFET
Gated Resistor
16
0.6
14 0.4
0.00 0.01 0.02 0.03 0.04
Distance in the x-direction ( m)
22
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Doping concentration Short-channel effects:
Junctionless vs. Inversion-mode device

-4
10
5x5_L =10nm, t =2nm
gate ox
V =1.0V
-6
10 DS
V =50mV
-8 DS
10
-10
10
-12
10
DIBL S/S
-14
10
Junction-less : 48 mV 66.2 mV/dec
Inversion-mode : 153 mV 83.8 mV/dec
-16
10
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V)
23
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Drain Current (A)
Conduction modes
Accumulation
JLess
Inversion
Mode
Mode
24
www.tyndall.ieConduction modes
Inversion-
Inversion-
Junctionless
Accumulation-
Junctionless
Accumulation-
mode
ON:
mode
mode
ON:
mode
-Large body current
ON:
-Large body current
ON:
ON:
ON:
-Surface Accumulation
Main current in
-Surface Accumulation
Main current in
-Small body current
-Small body current
channels are
surface inversion
channels are
surface inversion
-Surface Accumulation
-Surface Accumulation
unnecessary
channels
unnecessary
channels
channels
channels
OFF:
OFF:
OFF:
OFF:
OFF:
OFF:
Body subthreshold
Surface subthreshold
Body subthreshold
Surface subthreshold
Body subthreshold
Body subthreshold
current
current
current
current
current
current
25
www.tyndall.ieWhen reaching quantum dimensions
Inversion-Mode
Junctionless
26
www.tyndall.ieBulk Mobility instead of Surface Mobility
27
www.tyndall.ieMobility vs. doping
28
www.tyndall.ieHigh Doping  Low Mobility (?)
Electrons Holes
Jacoboni, C., C. Canali, G. Ottaviani, and A. A. Quaranta, “A review of some charge transport properties of silicon”, Solid State Electron. 20, 2(1977) 77-89
29
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»
m »
m
» »
m
»
-
-
»
m
m
»
»
CV/I
assuming EOT = 1nm for JLess device
MOSFET Junctionless
T W
W
2
si si
si
I q N V
I C (V V )
DD
D D
D ox DD TH
L
L
C C W L
C C W L
ox si
ox si
2
2
CV C W LV L
ox si DD CV C W LV C L
ox si DD ox
W
I 2 V
T W
si
I q N T
DD si si
D si
C (V V )
q N V
ox DD TH DD
D
L
L
0
10
-1
10
-2
10
MOSFET
19 -3
Gated Resistor N =10 cm
D
-3
19 -3
10
Gated Resistor N =2x10 cm
D
19 -3
Gated Resistor N =3x10 cm
D
19 -3
Gated Resistor N =5x10 cm
D
19 -3
Gated Resistor N =8x10 cm
D
-4
10
Simulations
0 5 10 15 20
Gate length (nm)
30
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CV/I (ps)Acknowledgements
Tyndall’s Central Fabrication Facility
Tyndall’s Central Fabrication Facility
Tyndall’s Advanced Microscopy Facility
Tyndall’s Advanced Microscopy Facility
31
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