Compact Models of Multi Gate and Other Emerging Transistors

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Compact Models of Multi Gate and Other Emerging Transistors


Matthew Donizetti, MS EE candidate

Prof. Dimitris Ioannou, advisor


Department of Electrical and Computer Engineering

George Mason University


Tuesday 30 November 2010

9:00


10:
00 A.M.

Room 3202, Nguyen Engineering Building


Abstract


With the advent of mu
lti
gate and nanoscale fabrication techniques, seve
ral new transistor
topographies have been proposed and
manufactured
in the past decade. In parallel, accurate
and efficient compact models for these devices have been
likewise
developed. This
presentation

summarizes
select
topographies and their associated c
ompact models with a focus
toward computationally efficient models
constructed

for implementation in common modeling
languages such as Verilog
-
A and SPICE. Common
physical and mathematical
modeling
techniques have
also
been
reviewed

as has the evolution f
rom

simple multi gate devices to
nanoscale structures.

Device topographies to be discussed are double, triple, and cylindrical
gate MOSFETs, silicon nanowire FETs, and carbon nanotube FETs.