CMOS Transistor and Circuits

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Oct 2010

CMOS Transistor

1

CMOS Transistor and
Circuits

Instructed by Shmuel Wimer

Eng. School, Bar
-
Ilan University


Credits: David Harris

Harvey Mudd College


(Some materials copied/taken/adapted from

Harris’ lecture notes)

Oct 2010

CMOS Transistor

2

Outline


MOS Capacitor


nMOS I
-
V Characteristics


pMOS I
-
V Characteristics


DC characteristics and transfer function


Noise margin


Latchup


Pass transistors


Tristate inverter

Oct 2010

CMOS Transistor

3

Introduction


So far, we have treated transistors as ideal switches


An ON transistor passes a finite amount of current


Depends on terminal voltages


Derive current
-
voltage (I
-
V) relationships


Transistor gate, source, drain all have capacitance


I = C (
D
V/
D
t)

D
t = (C/I)
D
V


Capacitance and current determine speed


Also explore what a “degraded level” really means

Oct 2010

CMOS Transistor

4

MOS Capacitor


Gate and body form MOS capacitor


Operating modes


Accumulation




Depletion




Inversion

Oct 2010

CMOS Transistor

5

Terminal Voltages


Mode of operation depends on V
g
, V
d
, V
s


V
gs

= V
g



V
s


V
gd

= V
g



V
d


V
ds

= V
d



V
s

= V
gs

-

V
gd


Source and drain are symmetric diffusion terminals


By convention, source is terminal at lower voltage


Hence V
ds



0


nMOS body is grounded. First assume source is 0 too.


Three regions of operation


Cutoff


Linear


Saturation

Oct 2010

CMOS Transistor

6

nMOS Cutoff


No channel


I
ds

= 0

Oct 2010

CMOS Transistor

7

nMOS Linear


Channel forms



Current flows from d to s


e
-

from s to d



I
ds

increases with V
ds



Similar to linear resistor

Oct 2010

CMOS Transistor

8

nMOS Saturation


Channel pinches off




I
ds

independent of V
ds




We say current saturates




Similar to current source

Oct 2010

CMOS Transistor

9

I
-
V Characteristics


In Linear region, I
ds

depends on:



How much charge is in the channel



How fast is the charge moving

Oct 2010

CMOS Transistor

10

Channel Charge


MOS structure looks like parallel plate capacitor
while operating in inversion


Gate


oxide


channel


Q
channel

= CV


C = C
g

=
e
ox
WL/t
ox

= C
ox
WL


V = V
gc



V
t

= (V
gs



V
ds
/2)


V
t

(
V
gc



V
t

is the amount of
voltage attracting charge to channel beyond the voltage required for inversion
)

Oct 2010

CMOS Transistor

11

Carrier velocity


Charge is carried by e
-



Carrier velocity
v

proportional to lateral E
-
field
between source and drain



v

=
m
E


m

called mobility



E = V
ds
/L



Time for carrier to cross channel:


t

= L /
v

Oct 2010

CMOS Transistor

12

nMOS Linear I
-
V


Now we know


How much charge Q
channel

is in the channel


How much time
t

each carrier takes to cross

Oct 2010

CMOS Transistor

13

nMOS Saturation I
-
V


If V
gd

< V
t
, channel pinches off near drain


When V
ds

> V
dsat

= V
gs



V
t



Now drain voltage no longer increases current

Oct 2010

CMOS Transistor

14

nMOS I
-
V Summary


Shockley

1
st

order transistor models

Oct 2010

CMOS Transistor

15

Example


We will be using a 0.18
m
m process for your project


t
ox

= 40
Å



m

= 180 cm
2
/V*s


V
t

= 0.4 V


Plot I
ds

vs. V
ds


V
gs

= 0, 0.3, 0.6, 0.9, 1.2, 1.5 and 1.8V.


Use W/L = 4/2
l

Oct 2010

CMOS Transistor

16

Oct 2010

CMOS Transistor

17

pMOS I
-
V


All doping and voltages are inverted for pMOS


Mobility
m
p

is determined by holes


Typically 2
-
3x lower than that of electrons
m
n


Thus pMOS must be wider to provide same current


In this class, assume
m
n

/
m
p

= 2

Oct 2010

CMOS Transistor

18

Oct 2010

CMOS Transistor

19

DC Transfer Characteristics

V
tp



Threshold voltage of p
-
device

V
tn



Threshold voltage of n
-
device

Objective: Find the variation of
output voltage V
out

for changes in
input voltage V
in
.

Oct 2010

CMOS Transistor

20

Oct 2010

CMOS Transistor

21

Recall CMOS device

CMOS inverter characteristics is
derived by solving for V
inn
=V
inp

and
I
dsn
=
-
I
dsp

Oct 2010

CMOS Transistor

22

CMOS inverter is divided into five regions of operation

Oct 2010

CMOS Transistor

23

Oct 2010

CMOS Transistor

24

Oct 2010

CMOS Transistor

25

Oct 2010

CMOS Transistor

26

Oct 2010

CMOS Transistor

27

I
-
V Characteristics


Make pMOS is wider than nMOS such that

n

=

p

Oct 2010

CMOS Transistor

28

Current vs. V
out
, V
in

Oct 2010

CMOS Transistor

29

Load Line Analysis


For a given V
in
:


Plot I
dsn
, I
dsp

vs. V
out


V
out

must be where |currents| are equal in

Oct 2010

CMOS Transistor

30

Load Line Summary

Oct 2010

CMOS Transistor

31

DC Transfer Curve


Transcribe points onto V
in

vs. V
out

plot

Oct 2010

CMOS Transistor

32

Operating Regions


Revisit transistor operating regions

Region

nMOS

pMOS

A

Cutoff

Linear

B

Saturation

Linear

C

Saturation

Saturation

D

Linear

Saturation

E

Linear

Cutoff

Oct 2010

CMOS Transistor

33

Beta Ratio


If

p

/

n



1, switching point will move from V
DD
/2


Called
skewed

gate


Other gates: collapse into equivalent inverter

Oct 2010

CMOS Transistor

34

DC Transfer function is symmetric for
β
n
=
β
p

Oct 2010

CMOS Transistor

35

Oct 2010

CMOS Transistor

36

Noise Margin

It determines the allowable noise at the input gate (0/1)
so the output (1/0) is not affected

Noise margin is closely related to input
-
output transfer
function

It is derived by driving two inverters connected in series

Oct 2010

CMOS Transistor

37

Oct 2010

CMOS Transistor

38

Oct 2010

CMOS Transistor

39

Impact of skewing transistor size on noise margin

Increasing (decreasing) P / N ratio increases (decreases) the low
noise margin and decreases (increases) the high noise margin


Oct 2010

CMOS Transistor

40

Latchup in CMOS Circuits

Oct 2010

CMOS Transistor

41

Parasitic bipolar transistors are formed by substrate and
source / drain devices

Latchup occurs by establishing a low
-
resistance paths
connecting V
DD

to V
SS

Latchup may be induced by power supply glitches or
incident radiation

If sufficiently large substrate current flows, V
BE

of NPN
device increases, and its collector current grows.

This increases the current through R
WELL
. V
BE

of PNP
device increases, further increasing substrate current.

Oct 2010

CMOS Transistor

42

Oct 2010

CMOS Transistor

43

If bipolar transistors satisfy
β
PNP
x
β
NPN
> 1, latchup
may occur.

Operation voltage of CMOS circuits should be below
V
latchup
.

Remedies of latchup problem:

1.
Reduce R
substrate
by

increasing P doping of substrate
by process control.

2.
Reducing R
WELL

and resistance of WELL contacts by
process control.

3.
Layout techniques: separation of P and N devices,
guard rings, many WELL contacts (at design).

Oct 2010

CMOS Transistor

44

Pass Transistors


We have assumed source is grounded


What if source > 0?


e.g. pass transistor passing V
DD


V
g

= V
DD


If V
s

> V
DD
-
V
t

=> V
gs

< V
t


Hence transistor would turn itself off


nMOS pass transistors pull no higher than V
DD
-
V
tn


Called a degraded “1”


Approach degraded value slowly (low I
ds
)


pMOS pass transistors pull no lower than V
tp

Oct 2010

CMOS Transistor

45

Pass Transistor CKTs

As the source can rise to within a threshold voltage of the gate, the

output of several transistors in series is no more degraded than that

of a single transistor.

Oct 2010

CMOS Transistor

46

Transmission Gates


Single pass transistors produce degraded outputs


Complementary Transmission gates

pass both 0
and 1 well

Oct 2010

CMOS Transistor

47

Transmission gate ON resistance as input voltage
sweeps from 0 to 1(V
SS

to V
DD
), assuming that output
follows closely.

Oct 2010

CMOS Transistor

48

Tristates


Tristate buffer

produces Z when not enabled

EN

A

Y

0

0

Z

0

1

Z

1

0

0

1

1

1

Oct 2010

CMOS Transistor

49

Nonrestoring Tristate


Transmission gate acts as tristate buffer


Only two transistors


But
nonrestoring


Noise on A is passed on to Y

Oct 2010

CMOS Transistor

50

Tristate Inverter


Tristate inverter produces restored output


Violates conduction complement rule


Because we want a Z output

Oct 2010

CMOS Transistor

51

Multiplexers


2:1 multiplexer chooses between two inputs

S

D1

D0

Y

0

X

0

0

0

X

1

1

1

0

X

0

1

1

X

1

Oct 2010

CMOS Transistor

52

Gate
-
Level Mux Design





How many transistors are needed?
20

Oct 2010

CMOS Transistor

53

Transmission Gate Mux


Nonrestoring mux uses two transmission gates


Only 4 transistors

Oct 2010

CMOS Transistor

54

Inverting Mux


Inverting multiplexer


Use compound AOI22


Or pair of tristate inverters


Essentially the same thing


Noninverting multiplexer adds an inverter

Oct 2010

CMOS Transistor

55

4:1 Multiplexer


4:1 mux chooses one of 4 inputs using two selects


Two levels of 2:1 muxes


Or four tristates