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tunisianbromidrosisInternet και Εφαρμογές Web

5 Φεβ 2013 (πριν από 4 χρόνια και 6 μήνες)

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SIMICS Overview

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SIMICS


A Full System Simulator


Models disks, runs unaltered OSs etc.


Accuracy is high (e.g., pollution effects
factored in)


Simulates all benchmarks


Requires in
-
depth OS knowledge


paging, scheduling, even sendmail!


Bottom line
: System runs unmodified
instructions and code

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SIMICS


Features Snapshot


Multi
-
processor full system simulator


Processors are simulated at the instruction
-
set
level


Support for various ISAs, e.g., SPARC, x86, PPC,
ARM


Extensible


Mix and match architectures with operating
systems


Facilitates gathering of timing information


Extensible instructions


"bare bones" simulation possible

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Applications


Processor Design


MP architecture


OS Development and Emulation


Debugging


Memory hierarchy design

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SIMICS Architecture

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Breaking Down SIMICS


SIMICS Central



High
-
level architecture specification



Features


New device modules plug in to Simics framework



Simics API provides functions, interfaces, etc for user
extensions



Global time can be paused to inspect state


Access memory traffic or set breakpoints anywhere,


Checkpoint simulations


Timestamp user inputs

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SIMICS Central


Heterogeneous nodes can be connected into a
network using Simics Central


Synchronizes virtual time


Distributes simulated traffic between nodes


Imposes a minimum latency on all messages


Network simulation speed is limited by the
slowest process


Currently supports Ethernet networks

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Memory and I/O


Users can extend a simulated memory space
by adding a timing model (such as Ruby)


Simple cache models can be added to the base
simulator


Device models supported extensively


Keyboard/mouse controller, DMA, Interrupt
controller, floppy controller, Graphics cards, etc.


Users can write new device models

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Event Handling


Simics can mix event
-
driven and time
-
driven components


step queue and time queue


step queue


pc steps


time queue resolution


clock cycle

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SIMICS Slowdown


Best case 10X
-

100X


Limited statistics


Cache 1000X
-

10000X


in
-
order processor


Processor 10000X
-

1million


cycle
-
accurate


Implication



choose simulations wisely

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References


Micro 35 Tutorial:
http://www.cs.pitt.edu/~cho/cs2410/
currentsemester/handouts/simics_tuto
rial.pdf



http://www.artes.uu.se/events/summ
er01/magnusson2001
-
08
-
24.pdf