PVT miniproject - ApselLab

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7 Οκτ 2013 (πριν από 3 χρόνια και 9 μήνες)

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PVT
-
Invariant

Circuits
Mini
-
project

The objective of this project is to give you some flavor of how a process, supply voltage, and
temperature (PVT)
-
invariant circuit is designed.
In the fi
rst part, we will introduce
some
advanced
simulation tools in Caden
ce, such as Monte Carlo

simulation

and
corner simulation; in
the second part, we will walk you through a design problem that demonstrates various trade
-
offs
in PVT
-
invariant circuits.

Required Reading: “Device Mismatch and Tradeoffs in the Design of Analog

Circuits”, Peter R.
Kinget, JSSC, vol.40, no. 6, June 2005.

Suggested Reading: bicmos6HP Users’ Guide
, bicmos6HP Model Guide

Please read this assignment from the beginning to the end first before heading to Cadence.

Part I

The advanced simulation featur
es (i.e. Monte Carlo, corner) can only be used in ADE XL, a more
powerful tool than ADE L that you are
familiar

with. The following instructions will give you a
step
-
by
-
step guide to set up Monte Carlo and corner simulations in ADE XL. Feel free to explore

other cool

functions in ADE XL if you are interested.

1. Configure ADE XL:



Create a new schematic as shown above. Fo
r illustration purpose
s
, p
ut 1 pair of identically
-
sized
diode
-
connected
nfet
s
, 1 pair of
identically
-
sized
diode
-
connected
pfet
s
, and 1

pair of identically
-
sized resistors (
oppcpres

from bicmos6HP library) in the schematic.
B
ias
the instances (nfet, pfet,
or resistor)

in each pair with the same DC voltage (2.5V in the example).

Note that V0 through
V5 are 0V voltage sources for DC current

measurement only.

Lau
n
ch

ADE XL

.
Check

Create New View

, and then

OK

. In the new pop
-
up window,
make sure the View is

adexl

, and click

OK

.


A new window layout will appear:


Click the

Create Test


panel icon in the
top

left corner. Click

O
K


in the pop
-
up window.

You will now see the

ADE XL Test Editor


that looks a lot like

ADE L

.
We want to set up the
following
:

1) Setup
-
>Model Libraries (include the model libraries for bicmos6HP in the correct order)

2) Analyses
-
>Choose
-
>dc (activate
dc simulation only)

3) Output
-
>Setup (set up the outputs to measure the DC currents through the devices)

Since

ADE XL Test Editor


also allows you to load your saved state (Session
-
>Load State) in

ADE L

,
the best practice is to set up all the
se

configu
rations in

ADE L

, do a trial simulation
to make sure all the outputs are correctly evaluated or plotted, and save the state to load in

ADE
XL Test Editor

.

After completing the configuration, your window should look like this:


Be sure to check the

Pl
ot


and

Save


options for all the outputs. Close the

ADE XL Test
Editor

, and go back to the main adexl window. You should see the

Outputs Setup


Tab now
filled up. Locate the

panel icon at the top right corner. Make sure the pull
-
down options on its
left is selected as
.

Click on

to run a single simulation.

When the simulation is finished successfully, you should
see the

Nominal


column in the

Results


Tab is populated with the output measurements.

So far, you have configured

ADE XL


correctly.

If the simulation does not run or the output
results are not calculated, you should be able to debug the problem similar to what you would do
in

ADE L

.


2. Monte Carlo Simulation:

Pull down
, and select
.
Then click

Simulation Options



on the right
. The

Monte Carlo


window will pop up.


In

Method

,

Process


and

Mismatch


are two
types of device variation. To will illustrate their
difference, let

s do the following simulations.

1) Process only

Check

Process


first.

Set

Number of Points


to 20
. This indicates the number of Monte Carlo runs you are simulating.
Of course, the more points, the more accurate the statistics you get.

Usually 30 runs are the
minimum to get statistically significant results.

Check

Save
Process

Data


Check

Save Data t
o Allow Family Plots


Click OK.

Click on

will start the 20 Monte Carlo runs. Be patient and wait for all 20 simulations to
finish.

Histograms for all the outputs will pop up after the simulation. The statistics of the outputs are
also listed in the

Resu
lts


Tab, such as

Min

,

Max

,

Mean

, and

Sigma

.

Notice that the nfet pair have exactly the same

Min

,

Max

,

Mean

, and

Sigma

, and so do
the pfet pair, and the resistor pair. This is because by choosing

Process


in

Method

,
random
values are gen
erated for the
process parameters
in the device model, and it will affect the same
type of device of equally.

One particular
ly

meaningful plot to look at is the scatter plot.


Click

and choose

Scatterplot

. Select the nfet currents as the x
-
axis and
the y
-
axis. Note that
the scatter plot shows perfect correlation between these two currents.

2
) Mismatch only

Repeat the Monte Carlo simulation procedure for

Mismatch

. Check


Save Mismatch Data


this
time. Compare the difference in histogram and scatter
plot.

You will notice that now the nfet
currents are completely independent of each other, showing

mismatch


between identical
devices.

Selecting

All


in the

Method


section will include the effect of both

Process


and

Mismatch

.

Now that you know how

to run Monte Carlo simulation, complete the following assignments and
include the results in your report.

[Assignment
]

This part should be included in your report.

Assume W, L are the minimum width and length for a device (e.g.
use
W=
400nm, L=240nm for
n
fet

and
pfet,
use W=500nm, L=1um for
resistor).

Use Monte Carlo simulation to find out how
different sizing (4W/L, W/4L, 4W/4L) will impact
the normalized standard deviation (i.e.
sigma/mean
)

of the output currents in nfet, pfet, and resistor.

Simulate

P
rocess
”, “
Mismatch
”, and “All”

separately
. In each Monte Carlo setting, list mean,
sigma, and calculate sigma/mean in your reports for all the different sizes of all three devices.

Describe in your own words

the
impacts

of sizing on normalized standard dev
iation. Are there
differences in trends between “Process” and “Mismatch”.

3. Corner Simulation:

Corner
simulation

is often used to gauge the worst
-
case performance of the circuit at extreme
PVT corners.

ADE XL


allows you to set up any combination of PVT
conditions for corner
simulation.


Expand

Corner
s”

on the left panel, and then

Click to add corner

.

The

Corners Setup


window will pop up. For each corner, you can specify the combination of
PVT conditions, such as the temperature, the design variabl
es (VDD, load capacitance, etc.), and
a customized model library.

To

create a customized model file, copy design.scs file from


/opt/cadence
-
designkits/AMS/bicmos6hp/relHP/models/spectre

to your local directory for editing.

Open design.scs and search for t
he variable

cornr_nfet


and

cornr_pfet

. These two variables
can be set

to integers between
-
3 and +3, and they indicate

the
process skew for nfet and pfet
respectively. For
example
, while 0 means normal (typical) corner, setting cornr_nfet to +3
indicat
es high current, high speed nfet devices. It is the same with

cornr_nfet

,

cornr_pfet

,

cornr_res

,

cornr_cap

, and

cornr_ind

. For more detailed explanation, please refer to the
documentation file
bicmos6hp.users_guide.pdf

in


/opt/cadence
-
designkits
/AMS/bicmos6hp/relHP/doc

In this example, you can modify the values for

cornr_nfet

,

cornr_pfet

, and

cornr_res

, and
save and rename the modified design.scs file in your local directory.


For instance, setting

cornr_nfet=

+
3; cornr_pfet=

+
3; cornr_r
es=

-
3, I have defined a Fast
-
nfet,
Fast
-
pfet, Slow
-
resistor corner, which I will save as design_FFS.scs as the model file.

After creating the customized model files, we can now include it in the

Corners Setup

. In the

Model Files


section

Test/Custom M
odel


field,

Click to add

. In the pop up

Add/Edit Model
Files


window, include the customized model file

design_SSF.scs

,
AND


process.scs


from the
original design library. Then

OK

.

You can call this corner

FFS

, and click

to

Add/Update Corner

.

Once you have set up multiple corners, you can run

to obtain results
from all the corners.
From this point on, the simulation is quite straightforward, and you are
encouraged to explore more.


Part II

Most of the design considerations and principles in
this second part are based on Kinget

s 2005
JSSC paper. Please read it
thoroughly

before working on your design.

Design Scenario: Generating and mapping an accurate current on
-
chip is critical for integrated
systems. An often employed design to achieve thi
s goal
comprises of a voltage amplifier and a
current mirror

as shown below
.


Assume V
BG

is a process
-
invariant constant voltage

generated on
-
chip by bandgap reference
.
F
irst
inspection

suggests that the
absolute accuracy of
I
out

depends on the input offset of the amplifier,
the current mirror mismatch, the tolerance of the resistor, and, maybe to a lesser degree, the gain
of the amplifier.

In this design project, you are expected to investigate the trade
-
offs between
accuracy,

power, and bandwidth in a current generator design.

[Assignment]

Let
V
BG
=1.25V

and

V
DD
=2.5V.
Based on the above topology, design a current
generator such that the nominal value of I
out
=125uA.

A
nswer the following questions
in the report
before
starting to

work on

your design.

Pre
-
Design Questions:

1.
Among the factors listed from first inspection, which ones

in your opinion are the major
sources of variation that degrade accuracy of I
out
?


2. How would “Process” and “Mismatch” affect the circuit performanc
e differently

in this design
?

3.
In Kinget’s paper, DC accuracy (Acc) is defined as the RMS average value divided by its
standard deviation (sigma). So h
ow would you use Monte Carlo simulation to obtain accuracy
performance of your design?

4. For the volta
ge amplifier, do you prefer high gain or low gain? Why?

5. For the current mirror, do you prefer high output impedance or low output impedance? Why?

Write one paragraph or two
in your report
to explain your design strategy
.

Design goals
: the final design w
ill be evaluated by its figure of merits (FOM), defined
in
Kinget’s paper as
a function of bandwidth (
BW
), DC accuracy (
Acc
), and power (
P
)
:



In your report list bandwidth, accuracy, and power separately, and calculate the FOM.
You
are
also required to r
eport
separately
the
bandwidth, accuracy, power, and
FOM
for

the voltage
amplifier stage and the current mirror

stage
.

The accuracy should be simulated considering both
“Process” and “Mismatch”, i.e. the “All” option in “Method”. At l
east 50 points should b
e run in
Monte Carlo simulation to obtain statistically significant value.

In addition to the above
-
mentioned design goals, you should answer the following open
-
ended
questions in your report.

Post
-
Design Questions:

1. For both the v
oltage amplifier and the current mirror, what level are the output referred noises
in your design? Answer with noise simulation results and compare the noise value with the sigma
value you use for DC accuracy calculation.

2. Sweep V
DD

from 2.1V to 2.9V and

plot I
out

as a function of V
DD
. How much percentage change
in I
out

do you get over 32% change in V
DD
?

3. Sweep temperature from
-
20
o
C to 120
o
C

and plot I
out

as a function of temperature. How much
percentage change in I
out

do you get?

4.
Set up the corners

with different PVT combination (assume VDD is within the range of 2.1V
and 2.9V, and temperature is within the range of
-
20
o
C to 120
o
C). Which PVT combinations give
you the biggest and smallest I
out
? Explain why.