Wafer Cut and Rotation to Improve the Compound yield for 3D Wafer- on-Wafer Stacking

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1 Νοε 2013 (πριν από 3 χρόνια και 9 μήνες)

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Wafer Cut and Rotation to Improve
the Compound yield for 3D Wafer
-
on
-
Wafer Stacking


Bei

Zhang

Department of Electrical and Computer Engineering

Auburn University, AL
36849
USA

Thesis
Advisor:


Dr
.
Vishwani

D.
Agrawal

Thesis Committee
:
Dr. Victor
Nelson




Dr.
Adit

Singh





Dr. Charles Stroud


Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

2

3

Introduction


What’s 3D IC?











A chip in which two or more layers of active electronic
components are integrated horizontally or vertically

into


a single circuit.





Apr. 10, 2013

Bei’s

General exam


Wikipedia: http://en.wikipedia.org/wiki/Three
-
dimensional_integrated_circuit

4

Introduction


3D IC basic structure:













Apr. 10, 2013

Bei’s

General exam


Through silicon


Via (TSV)

Introduction


3D
Packaging?




3D transistor?












In

3D packaging, separate chips are stacked in a single package.
However, these chips are not
integrated into a single circuit.




Apr. 10, 2013

Bei’s

General exam

5

Introduction


Why 3D IC?











TSV connect the planar wafer in the vertical direction.


This reduces the need for long wires which in
turn


reduces the delay and power consumption.



Heterogeneous integration.



Reduced foot
-
print size,

desirable

in hand
-
held devices.

Apr. 10, 2013

Bei’s

General exam

6

Introduction


3D IC fabrication

methods:











Die on Die stacking (D2D)


Die on Wafer stacking (D2W)



Advantages : Higher yield, can stack only known good dies


Disadvantages: 1) Hard to handle and stack, Process expensive



2
) Low throughput


3) May not applicable to high
-
end systems


Wafer on Wafer stacking (W2W)


Advantages : 1) Highest throughput


2) Allows for highest TSV density


Disadvantages: Low compound stacking yield




Apr. 10, 2013

Bei’s

General exam

7

Introduction


Why compound yield loss in W2W stacking?











Apr. 10, 2013

Bei’s

General exam

8

Introduction


Wafers versus Layers in 3D W2W stacking











M.
Taouil
, S.
Hamdioui
, J.
Verbree
, and E.
Marinissen
, “On Maximizing the compound yield for
3D wafer
-
to
-
wafer stacked IC," in
Proc. International Test Conf
., 2010, pp. 1
-
10
.

Apr. 10, 2013

Bei’s

General exam

9

Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

10

Problem Statement


Conditions:


N number of repositories each with K wafers


Fault maps for all wafers based on pre
-
bond testing


A production size of M 3D ICs



Objective:


Maximize the overall compound yield



OR


Maximize the overall number of good 3D ICs



Apr. 10, 2013

Bei’s

General exam

11

Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

12

Previous

Efforts


Exploiting different repository replenishment schemes



Exploiting

various matching algorithms



Exploiting

different matching criteria



Exploiting more practical defect models



Specifically design wafers for matching



Apr. 10, 2013

Bei’s

General exam

13


Repository replenish schemes can be:



Static Repository


None of the repositories will be replenished until


they run out of wafers.




Running Repository


Each repository is immediately replenished with a new
wafer each time a wafer is selected.






Different Repository
S
chemes

M.
Taouil
, S.
Hamdioui
, J.
Verbree
, and E. J. Marinissen, “On Maximizing the compound yield
for 3D wafer
-
to
-
wafer stacked IC," in
Proc. International Test Conf
., 2010, pp. 1
-
10
.

Apr. 10, 2013

Bei’s

General exam

14


15


Matching algorithms based on Static repository
:

Matching Algorithms

S.
Reda
, G. Smith, and L. Smith, “Maximizing the Functional Yield of Wafer
-
to
-
Wafer 3
-
D Integration,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1357

1362, Sept. 2009.

Globally greedy matching

Iterative matching heuristic

Integer linear programming

Iterative greedy

16


Matching algorithms b
ased

on Running repository
:

Matching Algorithms


First in First out 1 (FIFO1)


First in First out n (
FIFOn
)


Best Pair (BP)

A general W2W matching framework can be found in
Taouil’s

ITC paper, 2010

17


Matching criteria
:

Matching Criteria


Maximize matching good dies


Maximizing matching bad dies


Minimize matching between good and bad dies (UF)

18


Illustration of two different kinds of wafer maps
:

More Practical
W
afer

M
aps

Uniform

Clustered

19


Wafers fabricated with rotational symmetry:

Specifically

D
esigned

Wafers

B. Zhang, B. Li, V. D.
Agrawal
, “Wafer cut and rotation to improve the compound yield for 3D
Wafer
-
on
-
Wafer stacking,“
Proc. International Test Conf
., 2013, submitted
.


E. Singh, “Exploiting
Rtational

Symmetries for Improved Stacked Yields in W2W 3D
-
SICs,” in Proc. IEEE 29th VLSI Test Symposium (VTS), 2011, pp. 32

37.

Double rotation

Fourfold rotation

Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

20

21


A hybrid stacking procedure and a new wafer manipulation
method:



Illustration of Our
E
fforts

B. Zhang, B. Li, V. D.
Agrawal
, “Wafer cut and rotation to improve the compound yield for 3D
Wafer
-
on
-
Wafer stacking,“
Proc. International Test Conf
., 2013, submitted
.


Common wafer cut into sectors


Wafer Cut

and Rotation

Apr. 10, 2013

Bei’s

General exam

22


Cut rotationally symmetric wafer to

sectors:


Wafer Cut

and Rotation

Apr. 10, 2013

Bei’s

General exam

23


Sub
-
wafers rotation
:


Wafer Cut

and Rotation

Apr. 10, 2013

Bei’s

General exam

24


Dis
cussion

on the number of cuts:


Wafer Cut

and Rotation

Places where no
die can be placed


Illustration of Die loss on a wafer

Apr. 10, 2013

Bei’s

General exam

25

Process Flow

Apr. 10, 2013

Bei’s

General exam

26

Summary


Different wafer manipulation methods
:


Names

Explanations

Basic

Two wafers are matched directly

Rotation4

Two wafers can be matched in 4

different ways due to rotational
symmetry

Rotation2

Two wafers can be matched in 2

different ways due to rotational
symmetry

Cut and Rotation4

(CR4)

Each wafer is cut to 4 sectors

and with each sector rotated for
matching

Cut

and Rotation2
(CR2)

Each wafer is cut to 2 sectors

and with each sector rotated for
matching

Apr. 10, 2013

Bei’s

General exam

27

Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

28

29

Experiments


We consider 200
-
mm wafers with


edge clearance set as 5 mm.











Three types of chips with different die sizes:


Type1: 31.8 mm2, dies per wafer is 804, overall yield is 80.04%,


Type2: 63.4 mm2, dies per wafer is 436, overall yield is 61.27%


Type3: 131.6 mm2, dies per wafer is 184, overall yield is 50.97%



Experiment

setup:


Experiments


A production size of 100,000 3D ICs is targeted in


all experiments for each type of chips.



The running repository based best
-
pair matching algorithm


is utilized in the experiment.



Employ Heap structure to speed up the matching process


Experiment

setup:


Apr. 10, 2013

Bei’s

General exam

30

Normalized yield versus radius for three types of chips

31

Defect Model
U
sed

1) Uniform defect model

2) Radial clustered degradation model:


Inner core yield

Type1: 88%

Type2: 80%

Type3: 70%


D.
Teets
, “A Model for Radial Yield Degradation as a Function of Chip Size,” IEEE Transactions


on Semiconductor Manufacturing, vol. 9, no. 3, pp. 467

471, 1996.

32

Comparison of Stacking
P
rocedures

on
U
niform

and
C
lustered

D
efect

M
odels


Number of stacked layers:

2


Yield comparison between Basic, Rotation2, CR2 for type 3 chip

33

Impact of Cut
N
umber and Rotation
N
umber on
C
ompound

Yield


Number of stacked layers:

3


Normalized yield versus repository size for type 3 chips

34

Impact of Total
N
umber of Stacked

L
ayers
on
C
ompound Yield



Repository size is set as 50


Normalized yield versus number of stacked layers for type 3 chip

35

Impact of
W
afer

Yield
on
C
ompound Yield



Repository size is set as 50


Normalized yield versus inner core wafer yield for type 3 chip

36

Impact of Production
S
ize

on Compound
Y
ield



Repository size

:
25


Normalized yield versus production size for type 3 chip

37

Exploit More
D
efect

M
odels

The spatial probability functions used

to generate the simulated Wafers.


Gray levels correspond to failure

probabilities ranging from

0 (white) to 1 (black)

G.
DeNicoao
, E.
Pasquinetti
, G.
Miraglia
, and F.
Piccinini
, “Unsupervised spatial pattern
classification

of electrical fail
-
ures

in semiconductor manufacturing,” in
Artif
. Neural Net
-
works
Pattern
Recognit
. Workshop, 2003, pp. 125

131.

38

Yield Comparison
B
etween

D
ifferent

S
tacking
P
rocedures

(b) Pattern 2

(c) Pattern 3

(a) Pattern 1

(e) Pattern 5

(f) Pattern 6

(d) Pattern 4

(h) Pattern 8

(
i
) Pattern 9

(g) Pattern 7

Impact of Number of Stacked
L
ayers

on Compound
Y
ield

(b) Pattern 2

(c) Pattern 3

(a) Pattern 1

(e) Pattern 5

(f) Pattern 6

(d) Pattern 4

(h) Pattern 8

(
i
) Pattern 9

(g) Pattern 7

39

Impact of Production
S
ize

on Compound
Y
ield

(b) Pattern 2

(c) Pattern 3

(a) Pattern 1

(e) Pattern 5

(f) Pattern 6

(d) Pattern 4

(h) Pattern 8

(
i
) Pattern 9

(g) Pattern 7

40

Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

41

Repository Pollution

(downside of running repository)


Phenomenon
:


As the production size increases (large production volume), the
compound yield of 3D stacked IC decreases continuously.


Reasons:


Unattractive wafers remain in the repository for many iterations,


occupying space, and in effect reducing the size of the repository


in the long run.


General solution:


Need a mechanism to force the unattractive wafers to leave the
repository in a timely manner.





M.
Taouil
, S.
Hamdioui
, J.
Verbree
, and E. J. Marinissen, “On Maximizing the compound yield
for 3D wafer
-
to
-
wafer stacked IC," in
Proc. International Test Conf
., 2010, pp. 1
-
10
.

Apr. 10, 2013

Bei’s

General exam

42

Repository Pollution

(downside of running repository)


Possible detailed solutions
:


Conduct running repository based matching and static repository


based matching, alternatively.



Expunge poor wafers/quadrants from the repository if they


have not been used after
n

tries, send them to a die stacking


process to make some use of them



Exploiting a mechanism to force the unattractive wafer leave


the repository at the same rate as they come in.



Utilize
partial repository
instead of running repository to reduce


pollution and also enhance the compound yield.






Apr. 10, 2013

Bei’s

General exam

43

Find
O
ptimal

N
umber of Cuts

(Current research is exploring this aspect)


In case of more than 4 cuts, two methods of placement
:





Placement method 1

Placement method 2

Apr. 10, 2013

Bei’s

General exam

44

# of Dies
P
er

Sector (DPS) Calculator


Placement method 1
:





Apr. 10, 2013

Bei’s

General exam

45

# of Dies
P
er

S
ector

(DPS) Calculator


Placement method 2:





Apr. 10, 2013

Bei’s

General exam

46

Relationship Between DPW and # of Cuts

---

Case Study


# of Type 1 dies per wafer
:





DPW V.S.

number of cuts for placement method 1 and 2

47

Relationship Between DPW and # of Cuts

---

Case Study


# of Type 2 dies per wafer
:





48

DPW V.S.

number of cuts for placement method 1 and 2

Relationship Between DPW and # of Cuts

---

Case Study


# of Type 3 dies per wafer
:





49

DPW V.S.

number of cuts for placement method 1 and 2

Typical Die
S
ize

http://www.geek.com/glossary/die
-
size/

Apr. 10, 2013

Bei’s

General exam

50

Comparison Between
T
wo

P
lacement

M
ethods



Case
S
tudies


12
-
inch wafer (# of cuts range from 4 to 8)
:





The dots

show the cases where method 1 outperforms method 2

Apr. 10, 2013

Bei’s

General exam

51

Comparison Between
T
wo

P
lacement

M
ethods



Case Studies


18
-
inch wafer
(# of cuts range from 4 to 8)
:
:





The dots

show the cases where method 1 outperforms method 2

Apr. 10, 2013

Bei’s

General exam

52

Presentation Outline



Introduction


Problem Statement


Previous efforts


Our efforts


Proposed a hybrid wafer stacking procedure


Proposed a new wafer manipulation method


Exploited more defect models


Die per sector calculator


Experimental results


Future work


Pollution elimination


Find the optimal number of cuts


Conclusion

Apr. 10, 2013

Bei’s

General exam

53

Conclusion

Apr. 10, 2013

Bei’s

General exam

54


Deal with the problem of low compound yield in W2W stacking


Proposes a hybrid W2W stacking scheme


Proposes wafer Cut and Rotation manipulation method for yield
improvement


Extensive experimental results validate the cut and rotation
method


Develop the die per sector calculator


Need to solve repository pollution


Need to find the optimal number of cuts




55

References

[1] R.
Beica
, C.
Sharbono
, and T.
Ritzdorf
, “Through Silicon Via Copper
Electrodeposition

for 3D Integration,” in Proc. 58th Electronic Components and
Technology Conference (ECTC), 2008, pp. 577

583.

[2] M. L. Bushnell and V. D.
Agrawal
, Essentials of Electronic Testing for Digital, Memory
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-
Signal VLSI Circuits. Springer, 2000.

[3] W. R. Davis, J. Wilson, S. Mick, J.
Xu
, H.
Hua
, C.
Mineo
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Sule
, M. Steer, and P.
D.
Franzon
, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE
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510, 2005.

[4] G.
DeNicoao
, E.
Pasquinetti
, G.
Miraglia
, and F.
Piccinini
, “Unsupervised spatial
pattern
classification

of electrical fail
-
ures

in semiconductor manufacturing,” in
Artif
.
Neural Net
-
works Pattern
Recognit
. Workshop, 2003, pp. 125

131.

[5] X. Dong and Y.
Xie
, “System
-
Level Cost Analysis and Design Exploration for Three
-
Dimensional Integrated Circuits (3D ICs),” in Proc. Asia and South
Pacific

Design Automation Conference (ASP
-
DAC), 2009, pp. 234

241.

[6] J.
Dukovic

et al., “Through
-
Silicon
-
Via Technology for 3D Integration,” in Proc. IEEE
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2.

[7] A. Gupta, W. A. Porter, and J. W. Lathrop, “Defect Analysis and Yield Degradation of
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-
State Circuits, vol. 9, no. 3, pp. 96

102,
Mar. 1974.

56

References (contd..)

[8] H.
-
H. S. Lee and K.
Chak
, “Test Challenges for 3D Integrated Circuits,” IEEE Design
& Test of Computers, vol. 26, no. 5, pp. 26

35, 2009.

[9] H. Liao, M. Miao, X. Wan, Y. Jin, L. Zhao, B. Li, Y. Zhu, and X. Sun, “
Microfabrication

of Through Silicon
Vias

(TSV) for 3D
SiP
,” in Proc. 9th International Conference on
Solid
-
State and Integrated
-
Circuit Technology (ICSICT), 2008, pp. 1199

1202.

[10] E. J.
Marinissen
, “Challenges and Emerging Solutions in Testing TSV
-
Based 2
1/2D
-

and 3D
-
Stacked ICs,” in Proc. Design, Automation & Test in Europe
Conference & Exhibition (DATE), 2012, pp. 1277

1282.

[11] J. V.
Olmen

et al., “3D Stacked IC Demonstration Using a Through Silicon Via First
Approach,” in Proc. IEEE International Electron Devices Meeting (IEDM), 2008, pp.
1

4.

[12] F. D. Palma, G. D.
Nicolao
, G.
Miraglia
, E.
Pasquinetti
, and F.
Piccinini
,
“Unsupervised spatial pattern
classification

of electrical
-
wafer
-
sorting maps in
semiconductor manufacturing,” Pattern
Recogn
.
Lett
., vol. 26, no. 12, pp. 1857

1865, Sept. 2005.

[13] M.
Puech
, J. M.
Thevenoud
, J. M.
Gruffat
, N.
Launay
, N.
Arnal
, and P.
Godinat
, “Fabrication of 3D Packaging TSV Using DRIE,” in Proc. Symposium on
Design, Test, Integration and Packaging of MEMS/MOEMS, 2008, pp. 109

114.


57

References (contd..)

[14] S.
Reda
, G. Smith, and L. Smith, “Maximizing the Functional Yield of Wafer
-
to
-
Wafer
3
-
D Integration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 17, no. 9, pp. 1357

1362, Sept. 2009.

[15] A. Rogers, Statistical Analysis of Spatial Dispersions. United Kingdom:
Pion

Limited,
1974.

[16] E. Singh, “Exploiting
Rtational

Symmetries for Improved Stacked Yields in W2W
3D
-
SICs,” in Proc. IEEE 29th VLSI Test Symposium (VTS), 2011, pp. 32

37.

[17] E. Singh, “Impact of Radial Defect Clustering on 3D Stacked IC Yield from Wafer to
Wafer Stacking,” in Proc. International Test Conference (ITC), 2012, pp. 1

7.

[18] L. Smith, G. Smith, S.
Hosali
, and S.
Arkalgud
, “Yield Considerations in the
Choice of 3D Technology,” in Proc. International Symposium on Semiconductor
Manufacturing (ISSM), 2007, pp. 1

3.

[19] C. H.
Stapper
, “On Yield, Fault Distributions, and Clustering of Particles,” IBM
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338, 1986.

[20] C. H.
Stapper
, “Simulation of Spatial Fault Distributions for Integrated Circuit Yield
Estimations,” IEEE Transactions on Computer
-
Aided Design of Integrated Circuits
and Systems, vol. 8, no. 12, pp. 1314

1318, Dec. 1989.

[21] M.
Taouil

and
Hamdioui
, “Yield Improvement for 3D Wafer
-
to
-
Wafer Stacked
Memories,” Journal of Electronic Testing: Theory and Applications, vol. 28, no. 4, pp.
523

534, Aug. 2012.



References (contd..)

[22] M.
Taouil
, S.
Hamdioui
, J.
Verbree
, and E. J.
Marinissen
, “On Maximizing the
Compound Yield for 3D Wafer
-
to
-
Wafer Stacked ICs,” in Proc. IEEE International
Test Conference (ITC), 2010, pp. 1

10.

[23] D.
Teets
, “A Model for Radial Yield Degradation as a Function of Chip Size,”
IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 3, pp. 467

471,
1996.

[24] J.
Verbree
, E. J.
Marinissen
, P.
Roussel
, and D.
Velenis
, “On the Cost
-
Effectiveness
of Matching Repositories of Pre
-
Tested Wafers for Wafer
-
to
-
Wafer 3D Chip Stacking,”
in Proc. 15
th

IEEE European Test Symposium (ETS), 2010, pp. 36

41.

[25] T.
Yanagawa
, “
Influence

of Epitaxial Mounds on the Yield of Integrated Circuits,”
Proceedings of the IEEE, vol. 57, no. 9, pp. 1621

1628, Sept. 1969.

[26] T.
Yanagawa
, “Yield Degradation of Integrated Circuits Due to Spot Defects,” IEEE
Transactions on Electron Devices, vol. 19, no. 2, pp. 190

197, 1972.

[27] B. Zhang, B. Li, V. D.
Agrawal
, “Wafer cut and rotation to improve the compound
yield for 3D Wafer
-
on
-
Wafer stacking,“
Proc. International Test Conf
., 2013,
submitted
.

[28] B. Zhang and V. D.
Agrawal
, “Wafer cut and rotation for compound yield
improvement in 3D Wafer
-
on
-
Wafer stacking,”
Proc. 22nd North Atlantic Test
Workshop,
2013
.


58

References for Some Figures Used

[1]http://www.google.com/imgres?imgurl=http://i.i.com.com/cnwk.1d/i/tim/2011/05/04/intel
-
trigate
-
22nm
-
transistor
-
small.jpg&imgrefurl=http://news.cnet.com/8301
-
13924_3
-
20059431
-
64.html&h=385&w=439&sz=60&tbnid=EE_RELtUe5YAnM:&tbnh=90&tbnw=103&pre
v=/search%3Fq%3D3D%2Btransistor%26tbm%3Disch%26tbo%3Du&zoom=1&q=3D
+transistor&usg=__eiw39Fz1iYzP3WpUZgZZg7ILees=&docid=r1U7sbgV4MnNOM&h
l=zh
-
CN&sa=X&ei=OT9jUbrUOITS9QTLk4CYBw&ved=0CDEQ9QEwAA&dur=294

[2] http://www.google.com/imgres?imgurl=http://www.process
-
evolution.com/images_3d
-
ics/rpi_bcb_3d
-
ic.png&imgrefurl=http://www.process
-
evolution.com/3d
-
ics_doe.html&h=675&w=970&sz=262&tbnid=Kk9qMm4OzVTiJM:&tbnh=85&tbnw=12
2&prev=/search%3Fq%3D3D%2BIC%26tbm%3Disch%26tbo%3Du&zoom=1&q=3D+
IC&usg=__tCjabwl9UEVgdFUY57YsY4T6euM=&docid=4ieBYHE2oUKyMM&hl=zh
-
CN&sa=X&ei=ZD9jUeCxBoGY8gSSpIGABw&ved=0CDoQ9QEwAg&dur=44

59

Thank You!

60

Questions?