Memory Management - 西北工业大学

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1
2008-5-27 By GU/Jianhua NWPU 1
Memory Management
Memory Management
GU/
GU/
Jianhua
Jianhua
School of Computer Science
School of Computer Science
Northwestern
Northwestern
Polytechnical
Polytechnical
University
University
谷建华
谷建华
西北工业大学计算机学院
西北工业大学计算机学院
2008-5-27 By GU/Jianhua NWPU 2
Memory Management
Memory Management
Concepts
Concepts
Contiguous Allocation
Contiguous Allocation
Paging
Paging
Segmentation
Segmentation
Segmentation with Paging
Segmentation with Paging
Swapping and Overlay
Swapping and Overlay
2008-5-27 By GU/Jianhua NWPU 3
Background
Background


Program must be brought into memory and
Program must be brought into memory and
placed within a process for it to be executed.
placed within a process for it to be executed.

Process needs at least CPU and memory to run.

CPU context switching is relatively cheap.

Swapping memory in/out from/to disk is
expensive.

Need to subdivide memory to accommodate
multiple processes!
2008-5-27 By GU/Jianhua NWPU 4
Requirements for Memory Management


Allocation
Allocation


Address Binding
Address Binding

Protection and Sharing

Memory Hierarchy (Memory Extension)
2008-5-27 By GU/Jianhua NWPU 5
Memory Allocation
Memory Allocation


Why needed the memory allocated?
Why needed the memory allocated?


Program starting and finishing
Program starting and finishing


Program need more memory when executing
Program need more memory when executing


Program need changing its place
Program need changing its place


Allocation algorithms
Allocation algorithms


Single
Single
contiguous
contiguous
area
area
allocation
allocation

Partitioning

Paging

Segmentation


Segmentation
Segmentation with Paging
2008-5-27 By GU/Jianhua NWPU 6
Address Binding:
Address Binding:
Some Concepts
Some Concepts


Logical Address Space
Logical Address Space


Physical Address Space
Physical Address Space


Address Relocation: binding
Address Relocation: binding


Logical Address
Logical Address


Physical Address
Physical Address


Each binding is a mapping from one address space to another.
Each binding is a mapping from one address space to another.


Static and Dynamic Relocation
Static and Dynamic Relocation


Static: completed when compiling or loading
Static: completed when compiling or loading


Dynamic: Completed when running
Dynamic: Completed when running
-
-
time (need
time (need
hardware
hardware
memory
memory
-
-
management unit
management unit


MMU)
MMU)
2
2008-5-27 By GU/Jianhua NWPU 7
Memory
Memory
-
-
Management Unit (
Management Unit (
MMU
MMU
)
)


Hardware device that maps virtual to
Hardware device that maps virtual to
physical address.
physical address.


In MMU scheme, the value in the
In MMU scheme, the value in the
relocation register is added to every
relocation register is added to every
address generated by a user process at
address generated by a user process at
the time it is sent to memory.
the time it is sent to memory.


The user program deals with
The user program deals with logical
logical
addresses; it never sees the
addresses; it never sees the
real
real
physical
physical
addresses.
addresses.
2008-5-27 By GU/Jianhua NWPU 8
Maps Virtual to Physical Address
Maps Virtual to Physical Address
2008-5-27 By GU/Jianhua NWPU 9
Binding of Instructions and Data to Memory
Binding of Instructions and Data to Memory


Compile time
Compile time
:
:
If memory location known a
If memory location known a
priori, absolute code can be generated; must
priori, absolute code can be generated; must
recompile code if starting location changes.
recompile code if starting location changes.


Load time
Load time
:
:
Must generate
Must generate
relocatable
relocatable
code if
code if
memory location is not known at compile time.
memory location is not known at compile time.


Execution time
Execution time
:
:
Binding delayed until run time
Binding delayed until run time
if the process can be moved during its execution
if the process can be moved during its execution
from one memory segment to another. Need
from one memory segment to another. Need
hardware support for address maps (e.g.,
hardware support for address maps (e.g., base
base and
and
limit registers
limit registers).
).
Address binding of instructions and data to memory addresses can
happen at three different stages.
2008-5-27 By GU/Jianhua NWPU 10
2008-5-27 By GU/Jianhua NWPU 11
Dynamic Loading
Dynamic Loading


Loading
Loading
: from disk to memory
: from disk to memory


Routine is not loaded until it is called
Routine is not loaded until it is called


Better memory
Better memory
-
-
space utilization; unused routine
space utilization; unused routine
is never loaded.
is never loaded.


Useful when large amounts of code are needed to
Useful when large amounts of code are needed to
handle infrequently occurring cases.
handle infrequently occurring cases.


No special support from the operating system is
No special support from the operating system is
required implemented through program design.
required implemented through program design.
2008-5-27 By GU/Jianhua NWPU 12
Dynamic Linking
Dynamic Linking


Linking postponed until execution time.
Linking postponed until execution time.


Small piece of code,
Small piece of code,
stub
stub
, used to locate
, used to locate
the appropriate memory
the appropriate memory
-
-
resident library
resident library
routine.
routine.


Stub replaces itself with the address of the
Stub replaces itself with the address of the
routine, and executes the routine.
routine, and executes the routine.


Operating system needed to check if
Operating system needed to check if
routine is in processes
routine is in processes


memory address.
memory address.
3
2008-5-27 By GU/Jianhua NWPU 13
Protection and Sharing


Multi program in memory
Multi program in memory


Boundary Register
Boundary Register


Key Code
Key Code
2008-5-27 By GU/Jianhua NWPU 14
Memory Hierarchy (Memory Extension)


Swapping and Overlay
Swapping and Overlay


Virtual Memory
Virtual Memory
2008-5-27 By GU/Jianhua NWPU 15
Allocation algorithms
Allocation algorithms


Contiguous Allocation
Contiguous Allocation


Single Partition Allocation
Single Partition Allocation

Partitioning


Paging
Paging


Segmentation
Segmentation


Segmentation with Paging
Segmentation with Paging
2008-5-27 By GU/Jianhua NWPU 16
Single Partition Allocation
Single Partition Allocation
– Relocation register contains value of
smallest physical address; limit
register contains range of logical
addresses – each logical address must
be less than the limit register.
– Relocation-register scheme used to
protect user processes from each
other, and from changing operating-
system code and data.
– Be fit for single programmed, not for
multi programmed
2008-5-27 By GU/Jianhua NWPU 17
Single Partition Allocation
Single Partition Allocation


内存分为系统区和用户区。系统区仅
内存分为系统区和用户区。系统区仅
提供给操作系统使用;用户区指除系
提供给操作系统使用;用户区指除系
统区以外的全部内存空间,提供给用
统区以外的全部内存空间,提供给用
户使用。
户使用。


地址重定位时,只要将指令或数据的
地址重定位时,只要将指令或数据的
逻辑地址加上基地址,就可以形成物
逻辑地址加上基地址,就可以形成物
理地址。
理地址。


为了防止操作系统程序受到用户程序
为了防止操作系统程序受到用户程序
有意或无意的破坏,可以设置保护机
有意或无意的破坏,可以设置保护机
构。如,采用基址寄存器和界限寄存
构。如,采用基址寄存器和界限寄存
器机制。
器机制。


例如:
例如:
Dos
Dos
2008-5-27 By GU/Jianhua NWPU 18
Address Mapping
Address Mapping
Address Mapping for Single contiguous area allocation
Address Mapping for Single contiguous area allocation
4
2008-5-27 By GU/Jianhua NWPU 19
Partitioning

Basic Thoughts:

to divide memory into a number of partitions.
Each partition may contain exactly one process.
The degree of multiprogramming is bound by
the number of partitions
.

Fixed Partitioning

Dynamic Partitions
2008-5-27 By GU/Jianhua NWPU 20
Fixed Partitioning (1)

to divide memory into a number of fixed-sized
partitions. Each partition may contain exactly one
process.
2008-5-27 By GU/Jianhua NWPU 21
Fixed Partitioning (2)


Organization of memory: partition table
Organization of memory: partition table


Allocation algorithm
Allocation algorithm
if (Request <= Partition[i].size) allocation;
if (Request <= Partition[i].size) allocation;
else wait;
else wait;


Protection
Protection


Problem:
Problem: Internal Fragmentation.
Used
Used
308
308
k
k
32
32
k
k
2
2
3
3
Ava
Ava
.
.
300
300
k
k
8
8
k
k
1
1
State
State
Address
Address
Size
Size
No.
No.
2008-5-27 By GU/Jianhua NWPU 22
Dynamic Partitioning (1)

Partitions can be of variable length and number.

Process is allocated exactly as much memory as
requested.
2008-5-27 By GU/Jianhua NWPU 23
Dynamic Partitioning (2)


Dynamic partition allocation
Dynamic partition allocation


Hole
Hole –

block of available memory; holes of various
block of available memory; holes of various
size are scattered throughout memory.
size are scattered throughout memory.


When a process arrives, it is allocated memory from
When a process arrives, it is allocated memory from
a hole large enough to accommodate it.
a hole large enough to accommodate it.


Operating system maintains information about:
Operating system maintains information about:
a) allocated partitions OR b) free partitions (hole)
a) allocated partitions OR b) free partitions (hole)
OS
process 5
process 8
process 2
OS
process 5
process 2
OS
process 5
process 2
OS
process 5
process 9
process 2
process 9
process 10
2008-5-27 By GU/Jianhua NWPU 24
5
2008-5-27 By GU/Jianhua NWPU 25
2008-5-27 By GU/Jianhua NWPU 26
Dynamic Partition:
Dynamic Partition:
Organization of memory
Organization of memory


Key: how to organize the free partitions ?
Key: how to organize the free partitions ?


Linear list
Linear list


Linked List
Linked List
Used
Used
600k
600k
32
32
k
k
2
2
3
3
Ava
Ava
.
.
300
300
k
k
8
8
k
k
1
1
State
State
Address
Address
Size
Size
No.
No.
Size
Next
Size
Next
Size
Next
……
2008-5-27 By GU/Jianhua NWPU 27
Dynamic Partition Algorithms
Dynamic Partition Algorithms


First
First
-
-
fit
fit
: Ordering according to the
: Ordering according to the Address
Address. Allocate
. Allocate
the
the first
first hole that is big enough.
hole that is big enough.
Loop First
Loop First
-
-
fit
fit


Best
Best
-
-
fit
fit
: Ordering according to the
: Ordering according to the Size from small to
Size from small to
large
large. Allocate the
. Allocate the smallest
smallest hole that is big enough;
hole that is big enough;
Produces the smallest leftover hole.
Produces the smallest leftover hole.


Worst
Worst
-
-
fit
fit
: Ordering according to the
: Ordering according to the
Size from large
Size from large
to small
to small
. Allocate the
. Allocate the
largest
largest
hole. Produces the
hole. Produces the
largest leftover hole.
largest leftover hole.
How to satisfy a request of size n from a list of free holes.
First-fit and best-fit better than worst-fit in terms of speed
and storage utilization.
2008-5-27 By GU/Jianhua NWPU 28
Problems for Dynamic Partitioning
Problems for Dynamic Partitioning


Fragmentation
Fragmentation


Internal Fragmentation
Internal Fragmentation
: there is wasted space
: there is wasted space
internal to a partition due the fact that the block of
internal to a partition due the fact that the block of
data loaded is smaller than the partition. (Fixed)
data loaded is smaller than the partition. (Fixed)


External Fragmentation
External Fragmentation
: there are a lot of small
: there are a lot of small
holes in memory which is not used by process.
holes in memory which is not used by process.
(Dynamic)
(Dynamic)


Process need
Process need
Contiguous
Contiguous
memory
memory


Limited by the number of main memory
Limited by the number of main memory
2008-5-27 By GU/Jianhua NWPU 29
Compaction(
Compaction(
内存拼接)
内存拼接)


Four categories
Four categories
2008-5-27 By GU/Jianhua NWPU 30
Buddy System (1)
Buddy System (1)


In a buddy system, memory blocks are available of size 2
In a buddy system, memory blocks are available of size 2
K
K
,
,
L<=K<=U, where
L<=K<=U, where
2
2
L
L
: smallest size block that is allocated
: smallest size block that is allocated
2
2
U
U
: largest size block that is allocated; generally, 2
: largest size block that is allocated; generally, 2
U
U
is the size of the entire
is the size of the entire
memory available for allocation
memory available for allocation


Organization
Organization
: At any time, the buddy system maintains a list of
: At any time, the buddy system maintains a list of
holes (unallocated blocks) of
holes (unallocated blocks) of
each size 2
each size 2
i
i
.
.


Splitting
Splitting
: A hole may be removed from the (i+1) list by splitting
: A hole may be removed from the (i+1) list by splitting
it half to create two buddies of size 2
it half to create two buddies of size 2
i
i
in the
in the
i
i
list.
list.


Combine
Combine
: Whenever a pair of buddies on the
: Whenever a pair of buddies on the
i
i
list both become
list both become
unallocated, they are removed from that list and coalesced
unallocated, they are removed from that list and coalesced
(combined) into a single block on the (i+1) list.
(combined) into a single block on the (i+1) list.
6
2008-5-27 By GU/Jianhua NWPU 31
Buddy System (2)
Buddy System (2)


Allocation:
Allocation:
A request for an allocation of size
A request for an allocation of size k
k such that
such that
2
2
i
i
-
-
1
1
<
< k
k <= 2
<= 2
i
i
, the following recursive
, the following recursive
algorithm is used to find a hole of size 2
algorithm is used to find a hole of size 2
i
i
:
:
procedure get_hole(i);
procedure get_hole(i);
{ if (i>=U+1) failure;
{ if (i>=U+1) failure;
if (i_list is empty)
if (i_list is empty)
{
{
get_hole(i+1);
get_hole(i+1);
split hole into buddies;
split hole into buddies;
put buddies in i_list;
put buddies in i_list;
}
}
take first hole on i_list;
take first hole on i_list;
}
}
2008-5-27 By GU/Jianhua NWPU 32
Requirements for Memory Management


Allocation
Allocation


Address Binding
Address Binding


Protection and Sharing
Protection and Sharing


Memory Hierarchy (Memory Extension)
Memory Hierarchy (Memory Extension)
2008-5-27 By GU/Jianhua NWPU 33
Paging (1)
Paging (1)


Features of Partition
Features of Partition


Supporting multi
Supporting multi
-
-
programmed
programmed


Simple
Simple


Continuous space for each process
Continuous space for each process


Fragmentation
Fragmentation


Process size is limited by memory
Process size is limited by memory


Solution:
Solution:


Paging
Paging
2008-5-27 By GU/Jianhua NWPU 34
Paging (2)
Paging (2)


Logical address space of a process can be noncontiguous;
Logical address space of a process can be noncontiguous;


Divide physical memory into fixed
Divide physical memory into fixed
-
-
sized blocks called
sized blocks called
frames (size is power of 2, between 512 bytes and 8192
frames (size is power of 2, between 512 bytes and 8192
bytes).
bytes).


Divide logical memory into blocks of same size called
Divide logical memory into blocks of same size called
pages.
pages.


Keep track of all free frames.
Keep track of all free frames.


To run a program of size n pages, need to find
To run a program of size n pages, need to find
n
n
free
free
frames and load program.
frames and load program.


Set up a page table to translate logical to physical addresses.
Set up a page table to translate logical to physical addresses.


Internal fragmentation.
Internal fragmentation.
2008-5-27 By GU/Jianhua NWPU 35
illustration of paging
illustration of paging
Logical Address
(Pages)
[0]
[1]
[2]
[3]
[4]
Physical Address
(Blocks)
O S
80
81
82
83
84
86
87
88
89
UserProcess
[ 0 ][ 0 ]
85
UserProcess
[ 1 ][ 1 ]
[ 2 ]
[ 2 ]
[ 3 ]
[ 3 ]
[ 4 ]
[ 4 ]
Page Table
[ 0 ] -> 82
[ 1 ] -> 84
[ 2 ] -> 85
[ 3 ] -> 87
[ 4 ] -> 83
2008-5-27 By GU/Jianhua NWPU 36
Internal Fragmentation in Paging
Internal Fragmentation in Paging


Last frame allocated may not be completely full.
Last frame allocated may not be completely full.


Average internal fragmentation per block is typically half frame
Average internal fragmentation per block is typically half frame
size.
size.


Large frames vs. small frames:
Large frames vs. small frames:


Large frames cause more fragmentation.
Large frames cause more fragmentation.


Small frames cause more overhead (page table size, disk I/O)
Small frames cause more overhead (page table size, disk I/O)
7
2008-5-27 By GU/Jianhua NWPU 37
Address Translation Scheme
Address Translation Scheme


Address generated by CPU is divided
Address generated by CPU is divided
into:
into:


Page number
Page number
(p)
(p)


used as an index into
used as an index into
a
a page
page
table
table which contains base address
which contains base address
of each page in physical memory.
of each page in physical memory.


Page offset
Page offset
(d)
(d) –

combined with base
combined with base
address to define the physical memory
address to define the physical memory
address that is sent to the memory unit.
address that is sent to the memory unit.
2008-5-27 By GU/Jianhua NWPU 38
Address Translation Architecture
Address Translation Architecture
2008-5-27 By GU/Jianhua NWPU 39
P
P
D
D
P
P
CPU
Page table
RAM
P
P
P
P
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
D
D
D
D
D
D
P
P
ˊ
ˊ
P
P
ˊ
ˊ
D
D
D
D
D
D
Address Translation Process
Address Translation Process
P
P
ˊ
ˊ
2008-5-27 By GU/Jianhua NWPU 40
Paging Example
Paging Example
2008-5-27 By GU/Jianhua NWPU 41
Implementation of Page Table
Implementation of Page Table


Page table is kept in main memory.
Page table is kept in main memory.


Page
Page
-
-
table
table
base register
base register
(
(
PTBR) points to the
PTBR) points to the
page table.
page table.


Page
Page
-
-
table length register
table length register (PRLR) indicates size
(PRLR) indicates size
of the page table.
of the page table.


In this scheme every data/instruction access
In this scheme every data/instruction access
requires
requires two memory accesses
two memory accesses. One for the
. One for the
page table and one for the data/instruction.
page table and one for the data/instruction.
2008-5-27 By GU/Jianhua NWPU 42
Associative Register
Associative Register


The two memory access problem can be solved by the
The two memory access problem can be solved by the
use of a special fast
use of a special fast
-
-
lookup hardware cache called
lookup hardware cache called
associative registers
associative registers
or
or
translation look
translation look
-
-
aside buffers
aside buffers
(
(
TLBs
TLBs
)
)


Cache
Cache


Associative registers
Associative registers


parallel search
parallel search
Page #Frame #
8
2008-5-27 By GU/Jianhua NWPU 43
Fast Page Table
Fast Page Table


Function of
Function of
fast page table
fast page table
(FPT)
(FPT)


Address translation with FPT
Address translation with FPT


Use translation look
Use translation look
-
-
aside buffers (
aside buffers (
TLBs
TLBs
):
):
typically a few dozens entries.
typically a few dozens entries.


Hit ratio:
Hit ratio:
Percentage of time an entry is
Percentage of time an entry is
found.
found.


Hit ratio must be high in order to minimize
Hit ratio must be high in order to minimize
overhead.
overhead.
2008-5-27 By GU/Jianhua NWPU 44
Address translation with FPT
Address translation with FPT
2008-5-27 By GU/Jianhua NWPU 45
P
P
D
D
P
P
CPU
Fast Page table
RAM
P
P
P
P
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
D
D
D
D
D
D
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
D
D
D
D
Slow Page table
D
D
Address translation with FPT
Address translation with FPT


Hit
Hit
2008-5-27 By GU/Jianhua NWPU 46
P
P
D
D
P
P
CPU
Fast Page table
Fast Page table
RAM
RAM
P
P
P
P
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
D
D
D
D
D
D
D
D
D
D
Slow Page table
Slow Page table
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
P
P
ˊ
ˊ
D
D
Address translation with FPT
Address translation with FPT


Not Hit
Not Hit
2008-5-27 By GU/Jianhua NWPU 47
Effective Access Time
Effective Access Time


Associative Lookup =
Associative Lookup =
ε
ε
time unit
time unit


Assume memory cycle time is 1 microsecond
Assume memory cycle time is 1 microsecond


Hit ratio
Hit ratio


percentage of times that a page number
percentage of times that a page number
is found in the associative registers; ration related
is found in the associative registers; ration related
to number of associative registers.
to number of associative registers.


Hit ratio =
Hit ratio =
α
α


Effective Access Time (EAT)
Effective Access Time (EAT)
EAT = (1 +
EAT = (1 +
ε
ε
)
)
α
α
+ (2 +
+ (2 +
ε
ε
)(1
)(1


α
α
)
)
= 2 +
= 2 +
ε
ε


α
α
2008-5-27 By GU/Jianhua NWPU 48
Memory Protection
Memory Protection


Memory protection implemented by
Memory protection implemented by
associating protection bit with each frame.
associating protection bit with each frame.


Valid
Valid
-
-
invalid
invalid bit attached to each entry in
bit attached to each entry in
the page table:
the page table:




valid
valid


indicates that the associated page is in
indicates that the associated page is in
the process
the process


logical address space, and is thus
logical address space, and is thus
a legal page.
a legal page.




invalid
invalid


indicates that the page is not in the
indicates that the page is not in the
process
process


logical address space.
logical address space.
9
2008-5-27 By GU/Jianhua NWPU 49
Memory Protection Example
Memory Protection Example
2008-5-27 By GU/Jianhua NWPU 50
Multilevel Paging


Problem: Page tables can become very large!
Problem: Page tables can become very large!


Example: 32
Example: 32
-
-
bit address space (4GB) and 4kB page
bit address space (4GB) and 4kB page
size needs page table with 2
size needs page table with 2
20
20
entries!
entries!


Solution: Page the page table itself!
Solution: Page the page table itself!
2008-5-27 By GU/Jianhua NWPU 51
Two
Two
-
-
Level Page
Level Page
-
-
Table Scheme
Table Scheme
2008-5-27 By GU/Jianhua NWPU 52
Address
Address
-
-
Translation Scheme
Translation Scheme


Address
Address
-
-
translation scheme for a two
translation scheme for a two
-
-
level 32
level 32
-
-
bit paging architecture
bit paging architecture
2008-5-27 By GU/Jianhua NWPU 53
Shared Pages
Shared Pages


Shared code
Shared code


One copy of read
One copy of read
-
-
only (reentrant) code
only (reentrant) code
shared among processes (i.e., text editors,
shared among processes (i.e., text editors,
compilers, window systems).
compilers, window systems).


Shared code must appear in same location in
Shared code must appear in same location in
the logical address space of all processes.
the logical address space of all processes.


Private code and data
Private code and data


Each process keeps a separate copy of the
Each process keeps a separate copy of the
code and data.
code and data.


The pages for the private code and data can
The pages for the private code and data can
appear anywhere in the logical address space.
appear anywhere in the logical address space.
2008-5-27 By GU/Jianhua NWPU 54
Shared Pages Example
Shared Pages Example
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2008-5-27 By GU/Jianhua NWPU 55
Segmentation
Segmentation


Memory
Memory
-
-
management scheme that supports user
management scheme that supports user
view of memory.
view of memory.


A program is a collection of segments. A segment
A program is a collection of segments. A segment
is a logical unit such as:
is a logical unit such as:
main program,
main program,
procedure,
procedure,
function,
function,
local variables, global variables,
local variables, global variables,
common block,
common block,
stack,
stack,
symbol table, arrays
symbol table, arrays
2008-5-27 By GU/Jianhua NWPU 56
Logical Address Space from User View
Logical Address Space from User View
2008-5-27 By GU/Jianhua NWPU 57
Logical View of Segmentation (1)
Logical View of Segmentation (1)
1
3
2
4
1
4
2
3
user space physical memory space
2008-5-27 By GU/Jianhua NWPU 58
Logical View of Segmentation (2)
Logical View of Segmentation (2)


Program address space is divided by
Program address space is divided by
segmentation
segmentation


Give each segmentation a name,
Give each segmentation a name,
which is translate to segmentation
which is translate to segmentation
number
number


The size of segmentation is different
The size of segmentation is different


But a segmentation must be
But a segmentation must be
continuous
continuous
2008-5-27 By GU/Jianhua NWPU 59
Segmentation Architecture (1)
Segmentation Architecture (1)


Logical address consists of a two
Logical address consists of a two
tuple
tuple
:
:
<
<
segment
segment
-
-
number
number
,
,
offset
offset
>,
>,


Segment table
Segment table


maps two
maps two
-
-
dimensional
dimensional
physical addresses; each table entry has:
physical addresses; each table entry has:


base
base


contains the starting physical address
contains the starting physical address
where the segments reside in memory.
where the segments reside in memory.


limit
limit


specifies the length of the segment.
specifies the length of the segment.


flag
flag


read/write/execute privileges,
read/write/execute privileges,
validation
validation
bit
bit
2008-5-27 By GU/Jianhua NWPU 60
Segmentation Architecture (2)
Segmentation Architecture (2)


Segment
Segment
-
-
table base register (STBR)
table base register (STBR)
points
points
to the segment table
to the segment table


s location in memory.
s location in memory.


Segment
Segment
-
-
table length register (STLR)
table length register (STLR)
indicates number of segments used by a
indicates number of segments used by a
program;
program;
segment number
segment number
s
s
is legal if
is legal if
s
s
< STLR.
< STLR.
11
2008-5-27 By GU/Jianhua NWPU 61
Segment Address Translation
Segment Address Translation
2008-5-27 By GU/Jianhua NWPU 62
Segmentation Allocation
Segmentation Allocation


Since segments vary in length,
Since segments vary in length,
memory allocation is a dynamic
memory allocation is a dynamic
storage
storage
-
-
allocation problem.
allocation problem.


first fit/best fit algorithm is used
first fit/best fit algorithm is used


external fragmentation exist
external fragmentation exist
2008-5-27 By GU/Jianhua NWPU 63
Segmentation Protection
Segmentation Protection

Protection can be associated with segments.


With each entry in segment table associate:
With each entry in segment table associate:


validation bit = 0
validation bit = 0


illegal segment
illegal segment


read/write/execute privileges
read/write/execute privileges


Length of segmentation is limited;
Length of segmentation is limited; range
checks for arrays


Protection bits associated with segments;
Protection bits associated with segments;
code sharing occurs at segment level.
code sharing occurs at segment level.
2008-5-27 By GU/Jianhua NWPU 64
Segmentation Share
Segmentation Share


Code/Data sharing occurs at segment level
Code/Data sharing occurs at segment level
2008-5-27 By GU/Jianhua NWPU 65
A segmentation share example
A segmentation share example
2008-5-27 By GU/Jianhua NWPU 66
Segmentation with Paging
Segmentation with Paging


Problems of paging and segmentation
Problems of paging and segmentation


Program address space is divided by
Program address space is divided by
segmentation
segmentation


Physical address space is divided by paging
Physical address space is divided by paging


Address: ( s, p,
Address: ( s, p,
offset_of_page
offset_of_page
)
)


Address Translation (See Next)
Address Translation (See Next)
12
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Address Translation of
Address Translation of
Segmentation with Paging
Segmentation with Paging
2008-5-27 By GU/Jianhua NWPU 68
Overlay
Overlay
main():4K
fun3():9k
fun1():3K
fun2():5k
2008-5-27 By GU/Jianhua NWPU 69
Swapping
Swapping
OS