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27 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

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TUNED LNA FOR RFICs

USING
BOOT
-
STRAPPED

INDUCTOR

Fleana Albertoni, Luca Fanucci

, Bruno Neri, Enrico Sentieri

Università di Pisa, Dipartimento di Ingegneria dell’Informazione, Pisa, I
-
56122, Italy



C.S. Metodi e Dispositivi per Radiotrasmissioni, Consigli
o Nazionale delle Ricerche, Pisa, Italy


Index Terms



Tunable amplifiers, Inductors, Integrated circuit design, Bipolar analog integrated
circuits,
low
-
noise amplifier, radio frequency, wireless receiver


Abstract



In this paper, the principle of opera
tion of a new type of active inductor, based
on an integrated transformer in connection with a current amplifier, is described. The
application of this new scheme, named
boot
-
strapped

inductor, to the design of integrated tuned
low noise amplifiers (LNAs)
is demonstrated through actual measurement of a previously
developed prototype chip fabricated in a
20

GHz cut
-
off frequency bipolar process. The
measured center frequency of the amplifier is tunable between
0.96
-
1.026

GHz with a
transducer power gain grea
ter than
27

dB and a quality factor (
Q
) greater than
15
. Based on
the same
boot
-
strapped

inductor and on the same silicon technology, the design of an improved
LNA optimized at
1.8

GHz is presented. According to post
-
layout simulation the circuit features
a
60

MHz bandwidth, corresponding to a
Q

of
30
, a matched noise figure of
1.8

dB with
25.5

dB
transducer power gain and a power consumption of
20.7

mW from a
3

V power supply.

I.
I
NTRODUCTION

The realization of high quality factor (
Q
) integrated inductors

is one of the most intriguing problems
in the design of RF front
-
ends for integrated transceivers. In a previous work [1] the results which
can be obtained in terms of inductance (
L
) and
Q

values by using a novel circuit topology have been
described. Thi
s solution allows to obtain very high value of the
Q

x

L

product. Other solutions, based
on the utilization of active devices, have been proposed in the past to improve the
Q
-
factor with
respect to that of passive spiral inductors [2
-
3]. However, none of t
hese solutions is capable to
increase the effective
L

value which, in silicon integrated devices, is normally limited to a few
nanoHenry at frequencies of about
2

GHz. The approach proposed in this paper allows to improve
both the effective values of
L

and

Q
, almost up to a factor of
10
, while keeping practically constant
the occupied silicon area. This solution can be advantageously used to design tuned low noise
amplifiers (LNA) capable, for instance, of attenuate the image frequency by
20

dB @
200

MHz of

intermediate frequency. This has been already demonstrated by the authors in [4], where the design
and the simulation results of a preliminary tuned LNA based on the
boot
-
strapped

inductor are
presented.

The structure of this paper is as follows. Section
II presents the
principle of operation of the
novel
boot
-
strapped

inductor. In Section III, after a brief review of recently proposed LNA circuits, the
measurement of a previously designed tuned LNA prototype based on the
boot
-
strapped

inductor
approach a
re discussed. An improved LNA design optimized at
1.8

GHz is then described in
Section

IV while the relevant simulated performance results are presented in Section V together with
a comparison with previously proposed circuits. Finally, some conclusion ar
e drawn in Section VI.

II.
B
OOT
-
STRAPPED

INDUCTOR

In order to increase the
Q
-
factor of integrated inductors (defined as the ratio between the imaginary
part and the real part of its impedance) many techniques have been presented [5, 6]. Nevertheless it i
s
not simple to obtain
Q
-
factors greater than
8

for inductors of few nH. Indeed, achievable
Q

values
decrease as the inductor value rises. An improvement of
Q

can be obtained by using active circuits to
compensate for the losses of the integrated inducto
r [7]. This method, anyway, does not provide any
increase of the inductance value and it may lead to instability. Moreover, the robustness versus the
process parameter tolerances, and, consequently, their practical implementation, has not been
demonstrated

yet.

Here, we propose a solution based on the circuit depicted in Fig 1. This circuit exploits the magnetic
coupling between two spiral inductors (
L
1

and
L
2

in Fig.

1) to increase the inductance value seen at
the input terminals 1
-
1'. The inductor
L
3
, it
s parasitic series resistance
R
3

and the base
-
emitter
capacitance of
Q
1

realize an LRC filter. If the value of
L
3

is chosen in such a way to resonate with the
input capacitance of
Q
1
, then the current through
L
1

is in phase with the base
-
to
-
emitter voltage

of
Q
1
.
In this case, the currents
I
1

and
I
2

are in phase, provided that the equivalent transconductance
*
m
g

of
the cascode stage is a real value. Because of the magnetic coupling, the voltage drop on
L
1

is
increased by the factor
1
*
I
r
Mg
m


, where

is the operating frequency,
M

is the mutual inductance
between
L
1

and
L
2

and
r


is the base
-
to
-
emitter differential resistance of
Q
1
. In this case the value of
the equivalent inductance seen at the terminals 1
-
1' wo
uld be increased by a factor

r
Mg
m
*
. More in
general the input impedance seen at terminals 1
-
1’ (
Z
v
) is expressed by the following formula:

]
cos
[
]
[
*
1
*
1




















r
g
M
L
j
sin
r
g
M
r
R
Z
m
m
V

(1)

where
R
1

is the parasitic series resistance of
L
1

and


is the angle betwee
n
I
1

and
I
2
. This way the
equivalent inductance value is increased by a factor


cos
*
r
Mg
m
, whereas the real part is decreased
by




r
sin
r
Mg
m

*
. By changing

, which depends on the intrinsic capacitances of
Q
1

and
Q
2
,
different values of t
he effective inductance can be obtained. This task can be accomplished by
changing the bias current of
Q
1

and the base voltage of
Q
2

[1].

In Fig. 2 the performances of actual integrated inductors in Si
-
Ge technology [8], in terms of
Q

and
L
,
are compared
with the typical performance which has been obtained by using the new circuit block
depicted in Fig. 1, which has been called “
boot
-
strapped
” inductor.

III.

T
UNED
LNA

The LNA is the most critical stage as far as the overall noise figure (NF) of the receiv
er is concerned.
NF values as low as
2

dB are sometimes required in modern wireless terminals. In supereterodyne
architecture, which is, at present, the most widely adopted for this type of application, the LNA
should perform also another task: it should i
ntroduce a sufficiently large attenuation of the image
frequency. Indeed, presently realizable image rejection mixer are unable to obtain an image frequency
rejection larger than
40

dB, whereas some applications, for instance GSM standard, require overall
attenuation as high as
70

dB. To this end tuned amplifiers using high
Q

monolithic external filters
(ceramic or surface acoustic wave types) are required. The drawback of this solution consists of the
need of supplemental pins and external components whic
h are more costly and introduce noise and
attenuation also in the pass band. The realization of entirely integrated tuned amplifiers, in the GHz
range, represents a very stimulating target for RF IC designers. Several solutions have been proposed
in litera
ture using active inductors, realized by means of a gyrator [9, 10] or by shunting passive spiral
inductors with an active bipole presenting a negative resistance [11]. In all of these cases, the
Q

value
is quite low and the dissipated power and/or the no
ise figure are quite high. Moreover, the possibility
of compensating for the effect of the silicon process tolerances and of the temperature variations has
not been demonstrated. To this aim, the
boot
-
strapped

inductor technique presented in Section II ha
s
been recently used by the authors to design a tuned LNA characterized by values of the dissipated
power and of the noise figure suitable for wireless applications [4]. The circuit allows the control of
the amplifier center frequency in a range of about
60

MHz by means of two external voltages. It has
been realized in standard ST’s HSB2 bipolar process (a
0.4


m emitter width trench oxide isolated
bipolar process with three layers of metal and
20

GHz bjt’s cut off frequency) and some prototypes
have been
characterized in terms of frequency response. First measurements confirm the validity of
the
boot
-
strapped

inductor approach, even if a significant mismatch, about 40%, between simulated
and measured resonance frequency of the integrated
L
-
C

filter has bee
n observed. The most probable
cause of this mismatch is the poor confidence with the technological process as far as the
electromagnetic structures is concerned. Unfortunately, at the time of the design, no experimental
data were available coming from the

characterization of inductors and transformers in ST’s HSB2
technology, so it was not possible to validate the results of the electromagnetic simulations with real
data. However, the performances, as observed after measuring ten devices, are well repetiti
ve with the
typical spreading of the used silicon bipolar process. This result clearly indicates the presence of a
systematic error which should be easily eliminated by a more accurate dimensioning of inductors and
transformers.

The measured LNA transduce
r power gain (
G
T
), defined as the ratio between the power supplied to
the load and the available power at the input, is depicted in Fig.

3 versus frequency. The three curves
have been obtained by using the same device with different values of the external
control voltage.
The
measured center frequency of the amplifier is tunable between
0.957
and
1.027

GHz with a
transducer power gain always greater than
27

dB and a quality factor greater than
15
.
The
Q
-
factor
reaches its maximum value (
Q
max

=
30)
, at the
higher value of the explored frequency range (i.e.,
f
0
=

1.027
GHz for this sample). Ten devices have been characterized in order to give an indication of
the repeatability of the design and of the possibility of compensating process parameter tolerances by

means of external control voltages. The results of the test campaign are as follows: i) one sample
failed, ii) seven devices were tuned to the same nominal resonance frequency (that is
f
0
=
1.016

GHz)
with an attenuation greater than
15

dB at
1.216

GHz (tha
t is
200

MHz above
f
0
); iii) two samples
showed a slightly higher resonance frequency (about
1.09

GHz) which could be tuned to the nominal
value
f
0

(even using the external control voltages) only at the expenses of a degradation in the
selectivity (i.e. ac
cepting an attenuation lower than
15

dB). This means that, by using a
supereterodyne architecture with
100

MHz of intermediate frequency, and by considering the
aforementioned performance in terms of
f
0

and attenuation as a “pass/reject” criterion, the yie
ld of the
process would be
70
%.

Finally, a comparison between the measured performances and those previously reported in the
literature (measured and/or simulated) is summarized in Table I at the end of Section

V. The results
of this characterization, dem
onstrate the potentiality of the
boot
-
strapped

inductor technique in terms
of selectivity, stability, power dissipation, robustness of the design, controllability of the resonance
frequency
f
0

and yield.

IV.

HIGH Q, GAIN CONTROL
LED LNA

The main limit of t
he previously designed LNA based on the
boot
-
strapped

inductor [4], whose
characterization has been presented in Section III, is the reduced dynamic range: the simulated
1

dB
compression point amounts to

46

dB. To overcome this limit and also to improve
the selectivity and
the robustness versus process parameter tolerances and temperature variations, a new design has been
carried out. This new design and the relevant simulated performance results are addressed in this and
in the next Sections, respectivel
y. The new LNA circuit scheme is depicted in Fig. 4. It is based on a
transconductance stage to drive the current into a shunt
LRC

resonant filter, where
R

and
L


are the
real and the imaginary part of
Z
V

respectively, which is realized f
ollowing the
boot
-
strapped

inductor
approach described in Section II.

The input stage sets the noise figure of the amplifier, while the effective inductance value and the
quality factor
Q

of the
boot
-
strapped

inductor, can be controlled by means of
V
K

and

V
B2
. The
variable component of the current through
L
1

has a maximum at the frequency
f
0

at which the
LRC

filter resonates. The output stage is a current mirror which transfers this current, multiplied by the
current gain of
Q
OUT
, to the external load. A P
TAT (Proportional To Absolute Temperature) cell to
bias the input stage is used in order to counteract temperature variations effects on LNA voltage gain
(
A
v
). As it will be detailed in Section V, the voltage
Vc
, driven by a signal proportional to the LNA
output power level could be used to expand the LNA input dynamic range.

The amplifier is designed on ST’s HSB2 bipolar process.
The integrated transformer is made up by
two identical coupled inductors, the first one in metal 3, the second one in metal 2:
square shaped,
225


m per side, three turns each, metal track
10


m wide,
10


m spacing between adjacent metal
tracks. The inductor L
3

is also square shaped,
120


m per side,
2

turns in metal 3 (
10


m wide with
8


m spacing) in series with
3

turns in meta
l 2 (
8


m wide with
8


m spacing). A thick grid of trenches
underneath the inductors has been used to reduce the induced currents in the substrate, so allowing a
higher value of the Q
-
factor. The layout of the complete LNA is shown in Fig. 5 (where trench
es
underneath inductors were removed for a sake of clarity)
, the overall chip size is
0.52

mm
2

and it is
mainly due to the distance (nearly
400


m) between the transformer and the passive inductor, needed
to achieve a sufficient magnetic de
-
coupling betwe
en the two structures

[12].

V.

S
IMULATION AND
R
ESULTS

The electromagnetic simulation of the transformer and the passive inductor, is described in [13].
The extracted
Z

parameters of the equivalent circuit of the transformer were input to the Mentor
Graph
ics ELDO
TM

simulator to obtain the frequency response of the overall circuit. The transducer
power gain (
G
T
) is depicted in Fig.

6 versus frequency. These data are based on post
-
layout
simulations for the case of minimum NF matching.
G
T

reaches a peak val
ue of
25.5

dB at
1.8

GHz for
a band
-
width of
60

MHz, which results in a quality factor of
30
. This corresponds to an image
-
reject
filtering of
18.8

dB and
25

dB for a
100

MHz and
200

MHz intermediate frequency respectively.

One of the limiting factor in th
e utilization of highly selective integrated circuit is the
reproducibility of the results which is affected mainly by the spreading of the parameters of the active
devices. To this end the effect of the process tolerances have been simulated by using typi
cal, as well
as slow and fast models for bipolar transistors. In Fig. 7 it is shown as this effect can be quite
completely compensated by using the two control voltages
V
B2

and
V
K
. Particularly, the variation of
the resonance frequency and of the bandwidth

can be kept below
0.3
% and
5
% respectively, by
acting on
V
B2

and
V
K

and below
0.8
% and
5
% by using only V
K
.

By using the PTAT cell of Fig.

4, which determines a negligible silicon area increase, the LNA
voltage gain due to temperature variations in the

range [
0
ºC
-
80
ºC] is kept below
6.5
%.

The amplifier results unconditionally stable at least up to
5

GHz (the upper limit used for circuit
analysis). The minimum NF of the LNA, obtained through proper impedance matching with the input
signal source, is
1.8

dB and it is mainly due to the input stage according to the Friis formula.

Another very critical characteristic for wireless applications is the dynamic range, namely the
1

dB
compression point (CP
1dB
). The proposed circuit is characterized by a CP
1dB

of


50

dBm. By varying
the control voltage
V
C
, in the range [
2.6

V


2.9

V], it is possible to increase the input dynamic range
up to
-
20

dBm without any modification of the resonance frequency and of the bandwidth but at the
expenses of a voltage gain reduc
tion.

Finally in Table I a comparison among the main characteristics of silicon integrated tuned LNA
presented in literature and the solution described in this paper is shown. Also the measured data of the
previously designed LNA based on the
boot
-
strappe
d

inductor [4] are reported. To be noted that none
of these circuits have been optimized for an operating frequency higher than
1

GHz.

The ones with similar and/or higher selectivity than ours exhibit a NF from
2.5

to
4.2

dB higher and a
power consumption

greater than almost
3

to
4

times. Moreover, the proposed amplifier outperforms
the others in terms of voltage gain.

V.

C
ONCLUSION

The feasibility of tuned integrated LNAs using a new type of active inductor, named “
boot
-
strapped”

inductor, has been demons
trated
through actual measurement of a previously proposed
prototype chip based on the same approach.
Then a new design and post layout simulation results of
an improved version of tuned LNA have been presented. By using the novel
boot
-
strapped

inductor a
Q

value of
30

at
1.8

GHz has been obtained, while keeping the noise figure very close to its minimum
value compatible with the used bipolar silicon technology. The robustness of the design versus
temperature variations and silicon process tolerances have b
een also demonstrated. The integration of
such an LNA with a novel image rejection mixer [14] is currently pursued targeting to an integrated
RF front
-
end capable of attenuating more than
60

dB the image frequency without external
components. So the conven
tional bulky off
-
chip high Q
-
factor filter will not be longer required.

A
CKNOWLEDGEMENT

The financial support of the Italian National Research Council through the Finalized Project
“Materials and Devices for Solid State Electronics II” is gratefully ackno
wledged.

The authors specially thank David Nelli of Pisa University, Pisa, Italy for his invaluable support in
the measurements of the LNA prototypes.

R
EFERENCES

[1]

G. D’Angelo, L. Fanucci, A. Monorchio, A. Monterastelli, and B. Neri, “High Quality Active

Inductors”
, IEE Electronic Letters
, N. 20, pp. 1727
-
1728, September 1999.

[2]

H. Hayashi, M. Muraguchi, Y. Umeda; and T. Enoki , “A novel loss compensation technique for
high
-
Q broad
-
band active inductors”,
IEEE Microwave and Millimiter wave Monolithic Ci
rcircuits
Symposium

Digest
, pp.103
-
106, 1996.

[3]

Yei Li, B.L.Ooi, Q.J.Xu, and P.S.Kooi, "High Q active inductor with loss compensation by feedback
network",
IEE Electronic Letters
, N. 35, pp. 1328
-
1329, August 1999.

[4]

L. Fanucci, G. D’Angelo, A. Montera
stelli, M. Papero and B. Neri “Fully Integrated Low
-
Noise
-
Amplifier with High Quality Factor L
-
C Filter for 1.8 GHz wireless applications

Proc IEEE Int.
Symp. Circuits and Systems
, May 2001, Sidney, Austrialia.

[5]

J. N. Burghartz, K. A. Jenkins, M. Soyuer
: “Multilevel Spiral Inductors using VLSI Interconnect
Technology”,
IEEE Electron Device Letters
, Vol.

17, pp.

428
-
431, September 1996
.

[6]

F. Mernyei, F. Darrer, M. Pardoen, A. Sibrai: “Reducing The Substrate Losses for RF Integrated
Inductors”,
IEEE Micr
owave and Guided Wave Letters
, Vol. 8, pp. 300
-
301, September 1998
.

[7]

W. B. Kuhn, N.K. Yanduru, and A. S. Wyszynski: “Q
-
Enhanced LC Bandpass Filters for
Integrated Wireless Applications”,
IEEE Trans. MTT
, Vol. 46, pp. 2577
-
2586, December 1998.

[8]

L. E.
Larson, “Integrated circuit technology options for RF IC's
-

Present status and future
directions”,
IEEE Journal of Solid State Circuits
, vol.33, p.387
-
399, March 1998.

[9]

C. Y. Wu, and S. Y. Hsiao, “The Design of a 3
-
V 900
-
MHz CMOS Bandpass Amplifier”,
I
EEE
Journal of Solid
-
State Circuits
, vol. 32, no. 2, pp. 159
-
167, February 1997.

[10]

A. Thanachayanont, A. Payne:

“A 3
-
V RF CMOS Bandpass Amplifier using an Active
Inductor”
, Proc IEEE Int. Symp. Circuits and Systems
, vol. 1, pp. 440
-
443, May
-
June 1998, N
ew
York, USA.

[11]

W. Zhuo, J. Pineda de Gyvez, E. Sànchez
-
Sinencio:

“Programmable Low Noise Amplifier
with Active
-

inductor Load”
, Proc IEEE Int. Symp. Circuits and Systems
, vol. 4, pp. 365
-
368,
May
-
June 1998, New York, USA.

[12]

Y. Koutsoyannopoulos, Y.

Papanamos, S. Bantas, C. Alemanni:

“Novel Si Integrated Inductor
and Transformer Structures for RF IC Design”
, Proc IEEE Int. Symp. Circ. and Syst.
, vol. II, pp.
61
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64, May 1999, Orlando, Florida.

[13]

G. D’Angelo, A. Granchi, A. Monorchio, B. Neri: “Desi
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, pp. 1836
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1839, July 1999, Orlando, Florida.

[14]

G. Palmisano et al. “Integrated RF Image Rejection Mixer”,
unpublished.


LIST OF FIGURES

F
ig.
1
:

Boot
-
strapped

inductor

Fig. 2:

Q

versus
L

for SiGe spiral inductors [7]. Circle with dot represents a typical result
obtained by using the
boot
-
strapped

inductor described in this paper.

Fig. 3:

Transducer gain measurement
vs. frequency for the LNA prototype presented in [4] for
three different external control voltages.

Fig. 4:

Schematic of the new selective LNA.

Fig. 5:

Layout of the improved LNA.

Fig. 6:

LNA transducer gain vs. frequency based on post
-
layout simulations.

Fig. 7:

LNA transducer gain variation due to silicon process tolerances based on post
-
layout
simulations (slow, typical and fast process models).


LIST

OF

TABLES

Table I:

Proposed LNAs Comparison




Fig. 1:

Boot
-
strapped

inductor



Fig. 2:
Q versus L f
or SiGe spiral inductors [8]. Circle with dot represents a typical result obtained by
using the
boot
-
strapped

inductor described in this paper.








Fig. 3:

Transducer gain measurement vs. frequency for the LNA prototype presented in [4] for three
diff
erent external control voltages.





Fig. 4:

Schematic of the new selective LNA.




Fig. 5:

Layout of the new LNA.





Fig. 6:

LNA transducer gain vs. frequency based on post
-
layout simulations.



Fig. 7:

LNA transducer gain variation due to silicon pr
ocess tolerances based on post
-
layout
simulations (slow, typical and fast process models).



TABLE I

P
ROPOSED
LNA
S
C
OMPARISON



Technology

A
V

[dB]

NF

[dB]

f
0

[GHz]

P
d

[mW]

Q


[9]
M

CMOS

17

6

0.9

78

30

[10]
S

BiCMOS

18

4.3

1

57

56

[11]
S

CMOS

20

3.6

1

14

5

[4]

M

BJT

21.7
M

2.05
S

1
M

19.6
M

23.9
M

T
HIS

S

P
APER

BJT

22.5

1.8

1.8

20.7

30

M

Measured data

S

Simulated data