Phase 2 Report

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27 Νοε 2013 (πριν από 3 χρόνια και 10 μήνες)

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EE 5323 Project

16 Bit
Sklansky

Adder

Phase 2
Report

Yuan Xu

4139225

xuxxx488@umn.edu

Contents


Summary


Design Optimization & Changes


Waveforms of test cases


Schematic & Layout


maximum operating frequency VS. VDD


Power consumption at the maximum
operating frequency VS. VDD


Netlist


DRC,LVS results



Summary


The goal of this project is to realize 16bit
Sklansky

adder by using static CMOS devices.


Sklansky

adder belongs to tree adder family.



The difference between
Sklansky

adder and
other tree adders is prefix network.


Compare to other tree adders,
Sklansky

adder
has minimum logic levels, wiring tracks, but
maxinum

fanout
. Also, it has largest delay at
the same condition.

Summary

1:0
2:0
3:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
6:4
7:4
10:8
11:8
14:12
15:12
12:8
13:8
14:8
15:8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Structure of 16 bit
Sklansky

Adder

(Black square is dot operator

Grey square is empty dot operator

White triangle is buffer)


Reference List


D.Harris
, “ A Taxonomy of Parallel Prefix Networks,
Signals ”,
Systems and Computers, 2003. Conference Record of the Thirty
-
Seventh
Asilomar

Conference on, 2, 2213
-
2217 Vol.2,2003


J.
Sklansky
, “Conditional
-
sum addition logic,” IRE Trans. Electronic
Computers, vol. EC
-
9, pp. 226
-
231, June 1960.


J M.
Rabaey
, A.
Chandrakasan
, B.
Nikolic
, “ Digital Integrated
Circuits
-
A Design Perspective (Second Edition)”, Prentice Hall, 2003


Wu,S.D.,Chun
-
Chi Tsai,
Yang,M
, “A VLSI Layout Legalization
Technique Based on a Graph Fixing Algorithm”, VLSI Design,
Automation and Test, 2006 International Symposium on, 2006, 1
-
4


Mason, J.S.B.; , "Layout
tecbmques

for mixed
-
signal VLSI design,"
Systems on a Chip (Ref. No. 1999/133), IEE Colloquium on , vol., no.,
pp.8/1
-
8/11, 1999





Design Optimization and changes



Sizing the gate to minimum size (90nm)
reduces power


By using bubble shifting, we save totally 28
inverters, and 4 inverters on the critical path


Adding the buffer can effectively reduce delay.
Setting stage=1,
fanout
=4


Minimizing each block to reduce area


Combining VDDs of different devices to reduce
area



Design Optimization and changes


Combining
Nwell

and
Pwell

of different
devices to simplify the layout



Using fewer metal layers (2 layers) to reduce
complexity and capacitance


Changes: Fixing some flaws (body not
connected to ground) in schematic






Waveforms of test cases



Worst case: For Sklansky adder, the worst case
happens when inputs are 7FFF+0001. Since G
will propagate from A_0 to S_15 which is the
critical path.


Waveforms of test cases from layout


Worst case 7FFF+0001



A_0
-
A_15 B_0
-
B_15 Cout,S_0
-
S_15,


Waveforms of test cases from layout


Delay from A_0 to S_15 is 8.946E
-
10S

Waveforms of test cases from layout


FFFF+0002



A_0
-
A_15 B_0
-
B_15 Cout,S_0
-
S_15,


Waveforms of test cases from layout


Other cases(1111 0000, 0011 0045, 11FF EDAB, 9782 1234, AABB 5432, 1543 78AB,


FFFF FFEE, 1AB2 F182, 1BCD 2525,2312+4567,1278+AC00,FFFF+FFFF,4444+7777,
1894+2636,CC53+D126



A_0
-
A_15 B_0
-
B_15 Cout,S_0
-
S_15

Final schematic of adder



Final Layout

Area: 37.4
μ
m
×
11.8
μ
m

Maximum operating frequency for
different VDD! from layout

T=25C, 0.7, 0.3795

T=25C, 0.9, 0.759

T=25C, 1.1, 1.13

T=100C, 0.7, 0.24

T=100C, 0.9, 0.4689

T=100C, 1.1, 0.691

Frequency (GHz)

VDD! (v)

Frequency VS. VDD

T=25C
T=100C
Power consumption at the
maximum operating frequency at
different VDD


T=25C, 0.7, 0.12988

T=25C, 0.9, 0.41989

T=25C, 1.1, 0.931

T=100C, 0.7, 0.087154

T=100C, 0.9, 0.27835

T=100C, 1.1, 0.61588

Power (mW)

VDD (v)

Power VS. VDD

T=25C
T=100C
Circuit
netlist

from layout

and

modified runtestadder16b_xxx.sp

See attached files

Netlist

name is : new_16_bit_adder


Sizing


NMOS: L=50nm, W=90nm


PMOS: L=50nm, W=135nm


Temperature: 25
°
C

DRC Pass

LVS Pass