Massively Parallel Simulation

stingymilitaryΗλεκτρονική - Συσκευές

27 Νοε 2013 (πριν από 3 χρόνια και 6 μήνες)

54 εμφανίσεις

Time
-
Domain Segmentation based
Massively Parallel Simulation

Bichen

Wu

Dept. Micro/
nano

electronics

Tsinghua Univ., Beijing, China

Email:cunfuwbc@gmail.com

Mobile: +86 152 1056 0855

Background


On the one hand, transient circuit simulation is time
consuming


Sigma
-
Delta ADC: 71h



SAR ADC: 41h


FLASH ADC: 38h


PLL: 148h



On the other hand, we got strong parallel computing
resource


Many core, distributed computing




How can we increase the circuit simulation efficiency with
parallel computing?


Circuit simulation



T
ransient
circuit simulation is to solve the
initial
condition
problem of the following differential
equation





Backward Euler was used to convert the
above to sequence of discrete equations

Previous parallel circuit
simulation


Domain decomposition

A
New
Partitioning Method
for Parallel Simulation of VLSI Circuits
on Transistor Level

1996




Parallel numerical integral method

WavePipe
: Parallel Transient Simulation of Analog
and Digital
Circuits on Multi
-
Core Shared
-
Memory
Machines(DAC 2008)



Multi
-
algorithm parallel

Hierarchical
Multi
-
algorithm Parallel Circuit Simulation
(TCAD
2011)



Time domain segmentation
based parallel simulation


Method description

t
0

t
end

t
0

t
1

t
2

Time domain segmentation
based parallel simulation







In general, solution of equation is dependent
on initial condition



Uncertainty brought by time domain
segmentation may leads to erroneous result


Short memory assumption


Short memory


the
state of
the circuit at a certain time point
is correlated only to the
a

limited history of the the input as
well as the internal
state of
the circuit.



Circuits such as

ADC

possess short memory property


0
0
.
2
0
.
4
0
.
6
0
.
8
1
-
1
-
0
.
5
0
0
.
5
1
T
i
m
e
A
m
p
l
i
t
u
d
e


O
r
i
g
i
n
a
l

S
i
g
n
a
l
Q
u
a
n
t
i
z
e
d

S
i
g
n
a
l
A

D

Analog
input

Digital
output

Calculating SNDR through
transient simulation for ADC

A

D

Analog
input

Digital
output

Fourier
Transform

Power spectrum
density

Two examples

5
bits FLASH ADC

F
sam
=3.75GHz, T
total
=2us, T
ov
=6ns

Time for serial simulation

38h

Number of segmentation

1

2

4

8

100


6bits SAR
ADC

F
sam
=2GHz,
T
total
=8us
, T
ov
=13.3ns

Time for serial simulation

41h

Number of segmentation

1

2

4

8

100


Transient simulation for ADC

Power spectrum density of FLASH ADC(left) and SAR ADC

right

output, with serial and parallel simulation

FLASH

SAR

Transient simulation for ADC


Result

Transient simulation for

Sigma
-
Delta ADC


Sigma
-
Delta modulator

Because of integrator, it’s not short memory

Transient simulation for

Sigma
-
Delta ADC


Direct segmentation with the modulator
output of modulator brings erroneous
result

Time domain deviation
between serial and parallel
result

Frequency domain deviation
between serial and parallel
result

Transient simulation for

Sigma
-
Delta ADC


Uncertainty brought by time domain
segmentation

Transient simulation for

Sigma
-
Delta ADC

Digital filter
realized in
matlab


Solution:

Transient simulation for

Sigma
-
Delta ADC


Result showed efficiency enhancement with high
accuracy

Transient simulation for PLL


Phase lock loop(PLL) is not short memory circuit


Self
-
driven system


Integral property





f[ ]


h
(t)

+

-

Transient simulation for PLL


Phase lock loop(PLL)

The expression of the phase growth in the
equation above is as follow.



Let



So we get:







Transient simulation for PLL


Phase lock loop(PLL)






Transient noise analysis


PSD of 1/f noise generated in serial and parallel


Parallel:

Serial

The
bandwidth
gets wider

Transient noise analysis


1/f noise in TDSM



serial


parallel

Summary


We proposed TDSM for transient circuit simulation


Testified on FLASH

SAR

Sigma
-
Delta ADC



Maximum 78X acceleration with 100 cores parallelization



Efficient for phase noise simulation for PLL, testified by
behavior model.





Proposed 1/f noise generator that support TDSM, testified
on a single transistor



Now submitted to DAC 2013