# EE 416/516 VLSI DESIGN II

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27 Νοε 2013 (πριν από 4 χρόνια και 5 μήνες)

167 εμφανίσεις

1

E E 4 1 6/5 1 6 V L S I DE S I GN I I

D r. J.A. S t a r z y k

M i d t e r m

T h u r s d a y, M a y 4, 2 0 0
6

T H I S I S A T A K E H O M E E X A M

N a m e:

B o x #:

N o t e:

1 ) A l l s c r a t c h a n d p r o b l e m p a p e r s
m u s t b e t u r n e d i n.

2 ) E s t i m a t e d t i m e s r e q u i r e d t o c o m p l e t e p r o b l e m s a r e i n d i c a t e d.

P r o b l e m

We i g h t

E x a m i n e r' U s e

(points)

only

________________________________________________________

1

20

2

20

3

20

4

20

_________________________________________________________

TOTAL

80

2

Problem 1.
Timing & Race Conditions

The following circuit
(Figure
1.)
consists of a source portion, which adds the outputs of
two registers

R1 & R2 and a destination portion, which stores the sum in R3. The
connectio
ns

between the source and the destination are made by an automatic router,
which creates

wires with an average length of 1mm and containing an average of 10 vias
in series. This

each
wire.

A clock driver buffers the clock signal at the source and is routed by the same
tool to the

destination, where it connects to R3 and two other registers (R4 & R5) which
happen to

be close by. Each register presents a load of 300 fF to the clock drive
r.

Figure
1.

Assume the following timing values for the logic: t
carry
= 250 ps, t
sum
= 300 ps (including

setup
= 150 ps, t
hold
= 100 ps, t
clk
-
Q
= 50 ps.

a) Does this circuit have a race problem? What is the minimum clock period?

b) Wha
t if you removed R4 and R5? Would there be a race problem? What would the

new minimum clock period be?

c) What if the driver were placed at the destination (with R3,

R4 & R5)? Would there be

a race problem? What would the new minimum clock period be?

3

Problem 2.
Logical Effort, Switching Activity

&
Power

Let’s evaluate the effect of logic choice on power dissipation. Circuit A is an AND4 implemented as a
NAND2 chain while Circuit B implements the same function us
ing a 4 input gate.

a)

Size circuit A and circuit B for minimum delay with C
in

of 3 fF and C
out

of 50 fF. Report your
answer in terms of the input capacitance seen at each gate.

b)

Given that P(A=0) = P(B=0) = P(C=0) = P(D=0) = 0.25, calculate the probability
of energy
consuming transitions P(0
→ 1) at the outputs of the gates in both circuits.

c)

Assuming both circuits are operating at 500 MHz, calculate the dynamic power consumption
of the circuit. Assume γ = 1, V
dd

= 2.5V, and only consider capacitances at the inputs and
output of the gates.

50 fF

A

B

C

D

Circuit A

A

B

C

D

50 fF

Circuit B

G1

G2

G3

G1

G4

G5

G6

G2

4

Pr
oblem 3. Latches & Timing

Consider the simple state machine shown above. A, B, and C represent combinational

logic blocks with the following properties:

t
minA

= 200 psec; t
maxA

= 1 nsec;

t
minB

= 300 psec; t
maxB

= 2 nsec;

t
minC

= 100 psec; t
maxC

= 0.5
nsec;

The L
-
units represent
positive
latches
clocked by

. L has a setup time of 150 psec and a delay of 250
psec (t
d
-
q

when latch is transparent).
T
c
-
q

is 100 psec and t
hold

is 100 psec.
The

clock

has a period
T
and
is high for a duration of
T
on
. The duty cycle of the clock hence equals 100
T
on
/
T
%
.

a)

Determ
ine the conditions on the clock necessary to avoid the occurrence of races.

b)

Determine the absolute minimum clock period for

this circuit to work correctly as well as the
maximum duty cycle.

5

Problem 4. Logical Effort & Power

A
B
C
Out
Clk
1
2
2
2
2
2
2
1
2
1
PMOS
:
2
NMOS
:
1
V
x

The circuit above is a Limited Switch Dynamic Logic (LSDL) NOR3 gate which is a circuit family
used in high performance datapaths. It is essentially a domino gate followed by a latch. The relative
sizing of the gates has been annotated on the schemati
c.

a)

What is the purpose of the shaded transistors?

b)

Assuming no propagation delay, complete the following ideal timing diagram.

Clk
A
B
C
V
x
Out

c)

Assuming that A=B=C=1, compare the activity factor at node
Out

to the activity factor at
node
V
x

w
hich would be the output of a standard domino logic gate. What can you infer about
the dynamic power consumption of static gates being driven by this gate compared to domino
logic?