EE213 VLSI Design Lab 4

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27 Νοε 2013 (πριν από 3 χρόνια και 6 μήνες)

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EE213 VLSI Design Lab 4

In the previous lab you designed a basic CMOS inverter.

You were asked to answer the
following questions:


What are the output rise and fall delays for the circuit you have designed?


By using the

facility in the simulation

window, determine the maximum
current flowing in the circuit during switching. At what point in the switching
cycle does this maximum occur?


By using the

facility, estimate the logic threshold voltage. (The logic
threshold voltage is the point wher
e the input and output voltages of the inverter
are the same; i.e. the point where it can be said to have switched from ‘ON’ to
‘OFF’ or
vice versa


Record also the inverter ratio; i.e. ratio between the length/width ratio of the pull
up (pMOS) transis
tor and the length/width ratio of the pull
down (nMOS)


Change the inverter ratio and repeat section (7). How does the logic threshold
voltage vary with the inverter ratio?

In this lab you are asked to prepare a detailed report addressing th
ese questions. Spend
time at the beginning of the lab revisiting / redoing the design and carrying out the tests
necessary to provide the data necessary to answer the questions.

Your report should have the following

Name, Student Number, Class

Title o
f Report

Description of the Design and Experiment

Methodology and Results for Each Question

Conclusions and Discussion

Reports should be emailed to

before the end of the lab.