ECE491/ECE599, Introduction to VLSI - Utk

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Introduction to VLSI

Spring 200

S.K. Islam, 303 Ferris Hall, 974

Office Hours
M 1:00
2:00 pm, TR: 1:30
3:30 pm

Teaching Assistants

for VLSI Laboratory: Nazmul Islam (


Ken Martin,
Digital I
ntegrated Circuit Design
, Oxford, University Press, 2000


Class handouts

SmartSpice manual set

Baker, Li, & Boyce,
CMOS Circuit Design, Layout, and Simulation
, IEEE Press, 1998.


Midtem Exams




Laboratory Assignments


Homework 5%

Final Project




Lecture Classes

will meet in Perkins
, from 340
4:55 pm on Tuesdays & Thursdays. Class
attendance is encouraged and strongly recommended.

VLSI Laboratory

Lab/Project policy

If you fail to hand in TWO or more labs you will be assigned an 'F' in the course regardless of
test average. If you fail to hand in the Project you will also be assigned an 'F' in the course regardless of test

For on campus students, all labs

will meet in Room 508 at Ferris Hall. VLSI Labs will meet at the following times:
Wed. 5:00
7:00pm, and Thurs 5:00
7:00 pm

All labs will involve probably approximately 1/2 hour of lecture before starting, so BE ON TIME! Unless otherwise
noted, labs will

be due at the beginning of your assigned lab period one week after the lab was handed out. Your
assigned lab hours are the ONLY time you are guaranteed a workstation in FH 508. You will NOT be allowed to
use a workstation during a normal period if you a
re not assigned that lab period. Outside of these lab hours, FH 508
workstations are available on a first
come, first
serve basis.

WARNING! If we find a workstation in FH 508 screen
looked by a VLSI student, 10
points will be deducted from that student's

last VLSI test grade. We do NOT have enough
workstations resources to allow screen

The labs are designed to give advanced undergraduates and beginning graduate students a working knowledge of
CMOS digital integrated circuit technology, circuit
design methodologies, including simulation and physical layout
of CMOS digital circuit structures. Cadence and HSpice will be used widely for circuit simulation.

Details of the Lab will be posted on the course website.

Lab 1: Introduction


2: Simulation of Inverter using Smart Spice.

Lab 3: Schematic Entry of Inverter & Simulation

Lab 4: Schematic Entry of Complex Gate (NAND, NOR or XOR)

Lab 5: Cadence Layout of Inverter

Lab 6: Layout Simulation & generating LVS (Lay
out vs Schematic)

Lab 7: Cadence Layout of Complex Gate (NAND, NOR or XOR)

Lab 8: Transistor Sizing & Rise Time, Fall Time calculation

Lab 9: Design of a Full Adder

Lab 10: Design of a Full Adder (contd.)

Final Project:

of a Flip
Flop (T Flip
flop, D Flip
flop, JK flip flop or JK Master Slave flip flop)

Course Topics:

Introduction to CMOS Circuits

CMOS Transistor Theory

CMOS Transistor Theory, CMOS Process Video

CMOS Processes

CMOS Layout

Transmission Gates and Fully
fferential Logic

Delay Characterization

Lathes, Flip
Flops and Synchronous System Design

Bipolar and BiCMOS Logic Gates

Standard Cell Methodology

Capacitance Characterization

Transient Analysis

Clocked Systems

Dynamic Logic

Integrated Memories

Academic Di
: Will

be tolerated and

will be given. It is the responsibility of the
student to review UT policy and procedures in this area since they will be strictly adhered to. Cheating will result in
an F in the course, and possible univer
sity sanctions.