Chip Multiprocessors

stingymilitaryΗλεκτρονική - Συσκευές

27 Νοε 2013 (πριν από 3 χρόνια και 4 μήνες)

51 εμφανίσεις


1

Chip
Multiprocessor
s

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[Swapna]

Organizing the last line of defense before hitting the memory wall for CMPs

Liu, C.; Anand Sivasubramaniam; Kandemir, M.;

High Performance Computer Architecture, 2004. HPCA
-
10. Proceedings. 10th Internatio
nal Symposium on

14
-
18 Feb. 2004 Page(s):176


185

(
papers_p
\
L2.pdf
)


[Sherif]

Transient
-
fault recovery for chip multiprocessors

Gomaa, M.; Scarbrough, C.; Vijaykumar, T.N.; Pomeranz, I.;

Computer Architecture, 2003. Procee
dings. 30th Annual International Symposium on

9
-
11 June 2003 Page(s):98


109

(
papers_p
\
ft.pdf
)


Evaluating the Imagine stream architecture

Jung Ho Ahn; Dally, W.J.; Khailany, B.; Kapasi, U.J.; Das, A.;

Computer Architectur
e, 2004. Proceedings. 31st Annual International Symposium on

19
-
23 June 2004 Page(s):14


25

(
papers_p
\
imagine.pdf
)


[Swapna]

Interconnections in Multi
-
Core Architectures: Understanding Mechanisms, Overheads and Scalin
g

Kumar, R.; Zyuban, V.; Tullsen, D.M.;

Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on

04
-
08 June 2005 Page(s):408


419

(
papers_p
\
multicore.pdf
)


[Swapna]

An architecture and com
piler for scalable on
-
chip communication

Jian Liang; Laffely, A.; Srinivasan, S.; Tessier, R.;

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Volume 12,


Issue 7,


July 2004 Page(s):711


726

(
papers_p
\
td
m.pdf
)


[Michel]

Fair cache sharing and partitioning in a chip multiprocessor architecture

Kim, S.; Chandra, D.; Solihin, Y.;

Parallel Architecture and Compilation Techniques, 2004. PACT 2004. Proceedings. 13th International Conference on

29 Sept.
-
3 Oct.
2004 Page(s):111


122

(
papers_p
\
fair.pdf
)


[Ruibin]

Synchroscalar: a multiple clock domain, power
-
aware, tile
-
based embedded processor

Oliver, J.; Rao, R.; Sultana, P.; Crandall, J.; Czernikowski, E.; Jones, L.W., IV; Fr
anklin, D.; Akella, V.; Chong, F.T.;

Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on

19
-
23 June 2004 Page(s):150


161

(
papers_p
\
pa_tiles.pdf
)


[Shuyi]

Optimizing array
-
intensive appli
cations for on
-
chip multiprocessors

Kadayif, I.; Kandemir, M.; Chen, G.; Ozturk, O.; Karakoy, M.; Sezer, U.;

Parallel and Distributed Systems, IEEE Transactions on

Volume 16,


Issue 5,


May 2005 Page(s):396


411

(
papers_
p
\
array.pdf
)