AOI / AXI Development guidelines & ICT Development and Fixturing Specifications - Requirements

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Juniper Networks, Inc.


Page
1

of
21





AOI / AXI
Development
guidelines

&

ICT

Development

and Fixturing

Specifications

-

Requirements



Document Part Number: PROC
-
8425

Manufacturing Test Engineering

Version

7
.
0

May

21
, 2010
















AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
2

of
21


Table of Contents
:


Revision History

________________________________
________________________

2

1.

Automa
ted Optical Inspection

________________________________
________

3

2.

Automated X
-
ray Inspection

________________________________
_________

3

3.

ICT
Introduction
________________________________
___________________

5

4
.

ICT
Programming

________________________________
_________________

6


5
.

ICT Fixturing

________________________________
_____________________

9


5
.

ICT development quote package

________________________________
_____

17



Revision

Date

Revised By

Changes

.1

0
5
/
0
2/2005

James Lee

Initial Document Release

/
Incorporates
inputs from Westford.

.2

7
/
27
/2005

James Lee

Updated Digital Section to require Dual
Level Digital Thresholds.

Also updated
section on Voltage Regulators.

1.0

7/2
8
/2005

James Lee

Initial Agile Release.

2.0

1
1
/
30
/2006

James Lee

Added Requ
ir
ements for Duplicate Fixtures
and Fixturing Checklist.

Ad d
ed

Teststation
Configuration
. Some additional Teststation
specifics added.

Added Probe Table
s
.

3.0

7/17/07

James Lee

Updated Probe Table
. Added Quote and
Development File Package Requirements.

4.0

7
/
2
7
/0
9

James Lee

Ad
ded Bank 2 Requirement for 3070 and
other updates



5.0

10/27/09

Edward
Marden

Added AOI/AXI development guidelines
section

6.0

1/12/10

Edward
Marden

Added affectivity dates

to through hole AXI
requirements



7
.0

5/21
/
10

Edward
Marden

Changed the wording in regards to X
-
Ray
inspection to include all hidden joints.

Changed the wording in regards to solder
barrel fill to reference IPC
-
A
-
610
DC

as the
standard.



AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
3

of
21

Automated Optical Inspection
:



Supplier is expected to mai
ntain equipment, trained operators, and a system for
performing Automated Optical Inspection to include:


Equipment capable of automatically reviewing and identifying missing component,
proper orientation of components, tomb stoned components, and shorts a
t a minimum.



Inspection of 100% of components and 100% of visible solder joints on 100% of cards
assembled
.

Sampling is not allowed unless approved by Juniper.


OCR/OCV capabilities for specific applications as required


Inspection shall be performed af
ter SMT reflow.


All defects identified by system shall be captured.


All defects identified and repaired as true defects shall be captured separately


Note:

All parameters listed here may be
superseded

by Board Specific

Test Plans if
provided by Juniper T
est Engineering.


Automated X
-
ray Inspection


Supplier is expected to maintain equipment, trained operators, and a system for
performing Automated X
-
ray Inspection to include:


Equipment capable of automatically reviewing and identifying missing componen
t,
orientation of tantalums, tomb stoned components, shorts, opens, lifted pins, and voided
at a minimum.


All defects identified by system shall be captured
.


All defects identified and repaired as true defects shall be captured separately
.


Assemblies w
ill be inspected 100% of all
hidden joints.

Hidden joints are defined as those that cannot be visually inspected by the human eye or
AOI.

That includes but is not limited to,
BGA
s,

LGAs, TDFNs
,

ICs with ground pads and
solder pads underneath the IC.

This
inspection is required
on 100% of all cards assembled.


AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
4

of
21

Exceptions: On certain designs where ICT coverage

has been compromised for signal
integrity rules or when the net count of a board design exceed the capabilities of the ICT
test system, selective insp
ection of standard surface mount devices may be required as
dictated by the test plan.



Assemblies will be
inspected 100% of all press fit or through hole solder connectors

on
100% of all cards assembled.

This rule applies to all new NPI, effective Januar
y 1
st
, 2010.


Assemblies will be
inspected 100% of all through hole parts

on 100% of all cards
assembled.

This rule applies to all new NPI, effective January 1
st
, 2010.


All t
hrough hole solder connections must adhere to the IPC
-
A
-
610
DC

specification for
s
older fill requirements.


Inspection shall be performed immediate
ly prior to ICT
.


Program performed on Agilent X
-
ray
.


Note:

All parameters listed here may be
superseded

by Board Specific Test Plans if
provided by Juniper Test Engineering.



Programs will

be done in conjunction with Agilent standard practices with the following
exceptions:


Agilent
recommends

the following algorithms for voiding:

SENSITIVITY


0.15

MIN_VOID_DIA


10

PERCENT_VOID


30



Juniper
requires

the following algorithms for voiding:

SE
NSITIVITY


0.30

MIN_VOID_DIA


10

PERCENT_VOID


25


The sensitivity algorithm must always be set higher than the percent void for the voiding
algorithms to work properly. If the sensitivity is set lower than the percent void, the machine
will default to th
e sensitivity algorithm and therefore it will not take the percent void into
consideration. The MIN_VOID_DIA should be based upon the ball size.


Plastic Ball Grid Array Slice Requirements:

AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
5

of
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Juniper Networks requires a minimum of 2 slices using the

followi
ng

two
algorithms:

The first slice should be taken some value above the equator of the BGA ball to achieve between
65% and 70% up on the top of the ball. To determine where this slice should be set, follow the
Agilent procedure for Addendum defining “BGA2

First Slice Determination”. The second slice
should be taken from the component side of the PCB minus 5 mils (Top


5).


For all other BGA algorithms follow the Agilent procedure defining “BGA2 Algorithm Setup” and
best practices.



ICT

Introduction:

Th
e following list the minimum requirements for ICT Test Development and Fixturing.
Improvements on these minimums are encouraged but communications with Juniper is
required.
Items

/

component types not mentioned should assume “normal” ICT test
techniques

/

limits and fixturing practices.



Requirements for duplicate fixtures are also included

(see page
13
)
.


Please Note
: Fixturing Checklist to be completed by fixture vendor is at the end of this
document. Please print last 4 Pages for the Checklist.


No
te:

All parameters list
ed

here may be supers
eded by Board Specific

Test Plans if
provided

by

Juniper Test Engineering.


REFERENCE DOCUMENTS:



PROC
-
920
8



Juniper ICT NDF Process Improvement



PROC
-
9097



Contract Manufacturers ICT Changes Guidelines

AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
6

of
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Programm
ing:



Analog Limits should be set a follows
:

o

Resistors:



Use 4/6 wire measurements where necessary.



Tolerance Multiplier of 3 or less is recommended

(3070)
.



Less than 10 ohms, test as Jumper
.



Between 10 and 80 Ohms:



10 to 51 ohms +30%
,

-
2
%



52

to
80

ohms +25%
,

-

2
%



Between
81

ohms and 1 Meg ohms:



1%, test a
t

5%



5%, test at

10%



10%, test a
t

+15%,
-
10%



Larger than 10% Tol, test as specified by part



Greater than 1 Meg Ohms
,
test a
t

+15%,
-
10%



Pull Up/Downs, test a
t

+ /
-

12%

o

Capacitors:



50pF or smaller, +50%,
-
25%



Between 50pF and 10uF, test at + /
-

10%



10uf or larger, test at +40%,
-
20%



Caps rated at +80/
-
20, test at +80%,
-
20%

o

Inductors

/ Transformers
:



Measure if possible, otherwise, test as Jumpers

o

LED’s:



All “customer” visible LED’s are to include
“automate
d” o
ptical
c
olor and intensity checking

(using F
INN

/ Optomistic Sensors
)
,

o
r
otherwise specified by Test Plan.




All other LED’s should be tested
with
standard
Forward Voltage
Drop
test
methods.


o

Analog board grading will be used to verify all analog test
s are stable
with a CP
K

greater than
10

and all flagged t
ests are re
solved or
documented
.


Note: In general, use the tightest tolerance possible as dictated by circuit
configuration
s

while maintaining repeatability and stability.


AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
7

of
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Power Sequencing:

o

On
-
Boa
rd Supplied Power (bricks and such) should be used to power up
the board.



For FPC type boards, supply
-
48V and Bias

8
V, subsequence on
-
board power up sequencing should be done Higher Voltages to
Lower Voltages (i.e.
12v, then 5v, then 3.3v, etc
.



Some
b
oa
rd
s

power only using
-
48VDC.



Brick and Volterra Enables may need control via fixture
electronics (ie. Relays).



For PIC type boards, individual power rails will usually need to be
supplied by the tester (unless there is on
-
board power generation).
Again, P
ower from the highest voltage to the lowest.



Where Opto Isolators are used to Control Board Power,

use GP
-
Relays to control
the
Inputs of the Opto Isolator.



Consult Juniper Test Engineering for Power Up methodology
when in question.




Digital:

o

Please pay ca
reful attention to Logic Family/Levels (especially on Scan
Devices).

o

Utilize Dual Threshold Levels for all digital devices. Levels should be
able to detect the proper levels for high/low outputs of the device. For
example, set receive high at 2.0v and lo
w at 0.8v for 3.3 Volt Logic
Devices. Exceptions should be noted in the testplan and Juniper notified.

o

All devices without libraries or scan should be tested with Testjet

or VTEP

/

FrameScan

and Orientation

/

Presence check.

This is provided
the
c
omponen
t
s
tructure enables effective and repe
atable measurements to be
taken or as specified by ICT Test Plan (if provided).

o

Avoid the usage of standard Opens Express (prefer FrameScan or
FrameScan FX).

o

Eprom / Flash Memory contents should be CRC checked.

o

I2C EEP
ROM “custom” programming required (Assy #, Rev, SN, etc).
We have a custom utility that helps this effort.

o

All test libraries must be contained in the project directory. Utilize
Juniper Part Numbers as library names where feasible (3070 only).

o

Utilize Bo
undary Scan wherever possible.

AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


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Analog Functional:

o

Oscillators:



Measure
directly with tester
if possible. Divided down cl
ock
measurements are acceptable.



Utilization of
in
-
fixture clock dividers where necessary to
condition signals to be within testers m
easurement cap
a
bilities.



Signal Integrity requirements sometimes negate the placement of
Test Points on sensitive nets. In these cases, measurement of the
clock downstream may be necessary and preferred.


o

Voltage Regulators:



Measure all outputs. Limits +
/
-

5% or tighter.



Measure

at Power Up and exit on Failure is recommended to avoid
possible damage to board components.


Note:
On some Switching Regulators such as the Volterra VT202,
VT212 and VT223, you will likely need to remove some
probes from the “fe
edback” pins of the devices as they tend
to de
-
stabilize the regulators. Typical pin
function
names
are the “VX”, “VREF
_P
”, “VDES”, and “VFB
+
”.

o

Relays:



Electrically t
est
relays in
Energized and De
-
Energized Positions.




Connectors and Sockets:

o

Implement Te
stjet

/ Opens Express

(FrameScan)
where feasible. VTEP
(3070 only)

or FrameScan FX

may be usable but please check with
Juniper T
est Engineering
.




Program Modification Tracking:

o

All modifications to programs and fixtures after initial release must be
docume
nted and tracked in the Header Section of the TESTPLAN file.

o

Allowable CM Test Modifications are documented under PROC
-
9097
.




Test Coverage Grading
:

o

On 3070, Board Grader must be run with all identified marginal test
debugged accordingly.

Test coverage ana
lysis must be run after board
grader has been run
.

o

On TestStation, All Faults and Back Drive Reports must be provided.
All
identified marginal test must be debugged accordingly. Back Drive
measurements higher than 50mA must be addressed or justified to J
uniper.




NDF (No Defect Found):

o

Juniper requires NDF rates to be “ideally” no more than 8%. This number
is the number of ICT false failures as a percentage of the total ICT
AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
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failures. Improving NDF will improve the Yield, throughput and
efficiency of any I
CT test system. Refer to PROC
-
920
8

for reference.


Fixturin
g:



Unless otherwise specified, all 3070 Half Size Fixtures are to be developed to fit
onto Bank 2 (Left Side) of the tester interface.



Component Clearance:

o

There must be least 0.050" clearance i
n both the X
-

and Y
-
directions
between all pressure fingers and board components or leads (including
non
-
populated locations).

o

There must be least 0.050" clearance in both the X
-

and Y
-
directions
between all bottom
-
side board stops and board components or
leads
(including non
-
populated locations).

o

There must be least 0.050" clearance in the X
-
, Y
-

and Z
-
directions
between bottom
-
side components and the top plate. This also applies to
non
-
populated components.

o

There must be least 0.050" clearance in the X
-
,

Y
-

and Z
-
directions
between bottom
-
side components and the probe plate (and any other
support plates). This also applies to non
-
populated components.

o

There must be sufficient clearance in the fixture lid to accommodate
placement variations on large compon
ents (i.e. electrolytic caps, heatsinks,
daughter boards, etc). There must be at least 0.100" clearance between the
top of any component and the fixture lid when actuated. Ensure that
clearance for electrolytic caps allows for variation in the angle of the

component.

o

Provide documentation showing that the stack
-
up of the pressure finger
height, board thickness, and stopper height are correct
.

If it is necessary to
counter
-
bore the pressure fingers, provide calculations showing the bore
depth and proof that

the depth has been verified after the boring is
completed.




Board Flatness:

o

Proper Board Stress Analysis is required for all designs. Please notify
Juniper Test Engineering if Probe Density exceeds prudent fixture design
practices.

o

There must be sufficie
nt pressure fingers and board stops to keep the
board flat. There is no board flex occurring while the vacuum (or
pneumatic) is being actuated.

o

PTH leads have sufficient clearance so they do not come into contact with
the top plate (i.e. if milling of the
top plate is required, ensure it is deep
enough).


AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
10

of
21



Probe Requirements:

o

Probe travel (compression) is between .167" and .197". Documentation
indicating this check has been completed

and
must be supplied with the
fixture. At a minimum
,

the probe travel che
ck must be performed in the
center of the fixture, each quadrant of the fixture, and in high density
probe locations (>50 probes per ½" square).

o

Top
-
side probes do not come into contact with the UUT until the vacuum
or pneumatic is actuated. This is to pre
vent bending the probes along the
y
-
axis as the lid is closed.

o

In general, it is the responsibility of the fixture vendor to decide which
probe type is BEST for a given target

/ application
. However, we do have
the following
guidelines
:


NOTE: All probes
below reference the QA Probe Catalog Numbering.

Cross referencing will be necessary for other probe manufacturers.



QA
Standard Probes

Target

100 Mil

75 Mil

50 Mil

39 Mil

Vias / Pads

100
-
PRP2561x
-
S

0
75
-
PRP2561x
-
S

0
50
-
PRP2561x
-
S

0
39
-
PRP2543x
-
S

Open Hol
es

100
-
PRP25
03
x
-
S

0
75
-
PRP25
03
x
-
S

0
50
-
PRP25
03
x
-
S

0
39
-
PRP2543x
-
S

Thru
-
Hole w/
Lead Protrusion

< 0.018”

100
-
PRP2508x
-
S

0
75
-
PRP2508x
-
S

0
50
-
PRP2508x
-
S

0
39
-
PRP25
44
x
-
S

Thru
-
Hole w/
Lead Protrusion

> 0.018”

100
-
PRP2524x
-
S

075
-
PRP2524x
-
S

050
-
PRP2524x
-
S

039
-
PRP254
4x
-
S

Press
-
Fit
*
Connector Pins w/
Lead Protrusion

< 0.18”

100
-
PRP25
61
x
-
S

075
-
PRP25
61
x
-
S

050
-
PRP25
61
x
-
S

039
-
PRP25
43
x
-
S

Press
-
Fit
*
Connector Pins w/
Lead Protrusion

> 0.18”

100
-
PRP25
08
x
-
S

075
-
PRP25
08
x
-
S

050
-
PRP2544x
-
S

039
-
PRP2544x
-
S


QA X
-
Probes

Target

100 & 75 Mil

50 Mil

39 Mil

Vias / Pads

X75
-
PRP2561x
-
S

X50
-
PRP2561x
-
S

X39
-
PRP2561x
-
S

Open Holes

X75
-
PRP25
03
x
-
S

X
50
-
PRP25
03
x
-
S

X
39
-
PRP25
03
x
-
S

Thru
-
Hole w/ Lead Protrusion


< 0.018”

X75
-
PRP2508x
-
S

X50
-
PRP2508x
-
S

X39
-
PRP25
44
x
-
S

Thru
-
Hole w/ Lead Protrusio
n


> 0.018”

X75
-
PRP2524x
-
S

X50
-
PRP2524x
-
S

X39
-
PRP2544x
-
S

Press
-
Fit Connector Pins w/ Lead
Protrusion

< 0.18”

X75
-
PRP25
61
x
-
S

X50
-
PRP25
61
x
-
S

X39
-
PRP25
61
x
-
S

Press
-
Fit Connector Pins w/ Lead
Protrusion

> 0.18”

X75
-
PRP25
08
x
-
S

X50
-
PRP25
44
x
-
S

X39
-
PRP2544x
-
S


AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
11

of
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x

= Spring Force (Low, Standard, High) Rate. This will be Probe Density and Board
Stress dependent.




Recommend
ed

Probe Force

(@ 2/3 stroke)

Table:



Standard Steel Probes:



0.100”


5.5 oz.



0.075”


5.5 oz.



0.050”


5.5

oz.



0.039”


3.5

oz.



Low Force Probes (
if required):



0.100”


3.5 oz.



0.075”


3.1 oz.



0.050”


3.6

oz.



0.039”


3.0 oz.

o

QA’s X
-
Probe technology is preferred for 39 Mil Probing requirements.
Alternatively, “standard” 39 mil probes by QA

(039
-
16 Series)
.

o

For G
en
R
ad

wired fixtures, 26 AWG to 28
AWG solid twisted pair wiring

should be used for signal wiring. All power wiring will require at least 22
AWG stranded wire for interface to the ground or power planes

o

Wireless Fixturing Technology should be deploy
ed

on all fixtures with
2500 or more nets
. Implementation on smaller fixtures

will be

at the
discretion of Juniper Test Engineering.

o

*
PRESS
-
FIT connectors have in the past
,

been very challenging to
probe reliably due varying protrusion parameters

during
manufacturing
. There appears to be NO “o
ne probe fits all” solution
available. At this time, it is believe
d

that a general good starting
point is to use the
Blade
,
61

Style Probe with little to no lead
protrusion. Then
utilize a Crown 24

or 44

Style Probe
s

when there is
more protrusion
.
Afte
r this
, use

best
judgment
.




AOI/AXI Development Guidelines & ICT Development
and Fixturing Specifications
-

Requi
rements

Rev 7
.0

PROC
-
8425 Business Process


Juniper Networks, Inc


Page
12

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Operation and Mechanicals:

o

The fixture
must
actuate smoothly without binding and does not have any
air leaks or squeals. The board under test does not distort and remains flat
during actuation.

o

The board will NOT fit in the
fixture when rotated by 180°.

o

Implement “Cage” Guide Pins where required.

o

The fixture lid assembly can be locked

or

latched securely.

o

The center of gravity must be within the outline of the fixture base to
prevent the fixture from tipping.

o

Grooves (or chan
nels) should be cut into the top plate so the user can get
their fingers under the edges of the board (to make it easier to remove the
board from the fixture). These grooves should be on the long edge of the
board near the tooling pins.

o

Use ESD dissipative

materials where appropriate.

o

Implement Ground Plan
e

techniques where appropriate to suppress noise
and enhance signal integrity.

o

Fixtures should be designed to allow for Heat Sinks that are attached to
devices. This is provided Board Stress Profiles allo
ws for this.
Otherwise, please advise Juniper and we will make arrangements to have
Heat Sinks removed.

o

Push Down / Supports are NOT allowed on the lids of BGA devices (in
other words, don’t push directly on the BGA devices)

or on any Heat
Sinks that may
be mounted onto them
.




Safety:

o

When released from an angle of 45° or more, the fixture lid will remain in
the open position.

o

The fixture has a spring
-
loaded finger guard fitted to the interior to protect
against gas strut failure. This finger guard has rou
nded edges.

o

Protection is in place to prevent an operator's finger from being pinched
between the fixture lid and the top plate as the vacuum is actuated.

o

All exposed corners have rounded edges in order to reduce the risks of
pinch
-
points.




Label Requireme
nts:

o

All fixtures include these labels:



Fixture weight in both metric (kgs) and imperial (lbs) units
.



Autofile number

(3070 only)
.



Warning labels are placed on any non
-
ESD materials
.



Board
N
ame

and Board Assembly Number Label.



If supplied, Capital Asset La
bel.


AOI/AXI Development Guidelines & ICT Development
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Documentation:

o

Proof of Compliance to specs.

o

Probe types and quantities documented
.

o

Testjet

/ Opens Express

(FrameScan)

plate sizes and quantities
documented
.

o

Pressure finger and board stop sizes and locations documented. A map of
pressure fing
er lo
cations should be provided (dxf format).

o

Provide a paper copy of the quality checks performed on the fixture.

o

Provide documentation showing the results of the wiring verification.

o

Probe plots, bottom side board stop and milling, top side pressure fingers
d
rawings to be provided in electronic
(
dxf format
)
.

o

Test coverage report
.

o

Fixture Bom with manufacturers part numbers
.




Spare Parts and Additional Tools

(provided w/ fixture)
:

o

Probes.

o

Testjet plates.

o

Pressure fingers and stoppers.

o

Tooling pins.

o

Gaskets.

o

Sho
rting plate.

o

Plexiglas plate (registration plate), with probing locations partially drilled.

This can double as a dust cover.

o

All fixtures to include Electronic Cycle Counter.

o

Pressure finger validation plate with finger locations drilled out.

o

Plexiglas p
late (~0.100" thick) that has been fully routed in the same
locations as the top plate.


NOTE: BOLDED

items (last 2) may be unique to Juniper. Please
contact Juniper if there are any questions.




Duplicate Fixture Requirements:

o

Prior to duplicating fixtur
es, a
thorough

review of the TESTPLAN
Header Section of the current Production Testplan must be reviewed

by
the selected Programming Vendor
. Incorporate all fixture or program
affecting items.

o

Duplicate Program
s

(unless otherwise requested) must be set ba
ck to the
“Standard” Testmain Format, stripped of all CEM customization. Header
Section must include all items that affected the duplicate discovered in the
previous steps review.

o

All duplicate fixtures have the same deliverables requirements as for new
f
ixtures (documentation, inspection plates, etc.)

o

Completion of Fixturing Checklist is required (starting Page
18
).


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Tester
Type
Specific Parameters:



Agilent 3070 Specifics:

o

Use of VTEP may be possible (PLEASE ask firs
t).

o

Syntactically target 3070
-
PC Controller (even though test program may be
targeted for Unix Platform). Use “enable common delimiter” in the
3070’s board directory config file.

o

Autofile #, prefer the last 3 to 4 digits of the 710 (assembly #).

o

All test
libraries must be contained in the project directory. Utilize
Juniper Part Numbers as library names where feasible.

o

Full Board Grader Run,
verify all analog tests are stable with a CP
K

greater than
10

and all flagged tests are resolved or documented
.

o

Typi
cal 3070 Config File for Juniper
3070
Programs:


target hp3073 standard

enable software revision b

enable express fixturing

enable testjet

enable drivethru

enable advanced boundary scan differential

(as required)

enable silicon nails

(as required)

enable
common delimiter

enable advanced fixturing

enable 1149.6 boundary scan

(as required)

enable multiple board versions



module 0


cards 1 asru c revision


cards 2 hybrid standard double density


cards 3 hybrid standard double density


cards 4 hybrid standard double density


cards 5 hybrid standard double density


cards 6 control xt


cards 7 hybrid standard double density


cards 8 hybrid standard double density


cards 9 hybrid standard double density


cards
10 hybrid standard double density


cards 11 hybrid standard double density


end module



module 1


cards 1 asru c revision


cards 2 hybrid standard double density


cards 3 hybrid standard double density


cards 4 hybrid standard

double density


cards 5 hybrid standard double density


cards 6 control xt


cards 7 hybrid standard double density


cards 8 hybrid standard double density


cards 9 hybrid standard double density


cards 10 hybrid standard doub
le density


cards 11 hybrid standard double density


supplies hp6624 9 to 12 asru channels 1 to 4


end module



module 2


cards 1 asru c revision


cards 2 hybrid standard double density


cards 3 hybrid standard double density



cards 4 hybrid standard double density


cards 5 hybrid standard double density


cards 6 control xt

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cards 7 hybrid standard double density


cards 8 hybrid standard double density


cards 9 hybrid standard double density


c
ards 10 hybrid standard double density


cards 11 hybrid standard double density


supplies hp6624 5 to 8 asru channels 1 to 4


end module



module 3


cards 1 asru c revision


cards 2 hybrid standard double density


cards 3 hybri
d standard double density


cards 4 hybrid standard double density


cards 5 hybrid standard double density


cards 6 control xt


cards 7 hybrid standard double density


cards 8 hybrid standard double density


cards 9 hybrid stan
dard double density


cards 10 hybrid standard double density


cards 11 hybrid standard double density


supplies hp6624 1 to 4 asru channels 1 to 4


end module

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GenRad
TS128LX

Specifics:

o

TS128LX

Configuration


%System

Sys_name = WNEED08199
;

SYS_TYPE = TS128LSYS;

SYS_PIN_SLOTS = 30;

SYS_ACCESSORY_SLOTS = 1;

/* Serial_no = */

CPU_Type = PC;

OS_TYPE = XP;

8X_SW_Version = R_5_8_0;

Receiver_type = BED_OF_NAILS;



%RESOURCES

dig_control SYS_CNTRLR 1 SLOT=2;

/* Integrated System Controller*/

cst U
LTRACST 1 SLOT=2;

dig_control DSM 1 SLOT=2, MEMORY=256MB;

/* Pin boards 1
-
30;*/

pins ULTRA128L 1 SLOT=4;

pins ULTRA128L 2 SLOT=5;

pins ULTRA128L 3 SLOT=6;

pins ULTRA128L 4 SLOT=7;

pins ULTRA128L 5 SLOT=8;

pins ULTRA128L 6 SLOT=9;

pins ULTRA128
L 7 SLOT=10;

pins ULTRA128L 8 SLOT=11;

pins ULTRA128L 9 SLOT=12;

pins ULTRA128L 10 SLOT=13;

pins ULTRA128L 11 SLOT=14;

pins ULTRA128L 12 SLOT=15;

pins ULTRA128L 13 SLOT=16;

pins ULTRA128L 14 SLOT=17;

pins ULTRA128L 15 SLOT=18;

pins ULTRA1
28L 16 SLOT=19;

pins ULTRA128L 17 SLOT=20;

pins ULTRA128L 18 SLOT=21;

pins ULTRA128L 19 SLOT=22;

pins ULTRA128L 20 SLOT=23;

pins ULTRA128L 21 SLOT=24;

pins ULTRA128L 22 SLOT=25;

pins ULTRA128L 23 SLOT=26;

pins ULTRA128L 24 SLOT=27;

pins U
LTRA128L 25 SLOT=28;

pins ULTRA128L 26 SLOT=29;

pins ULTRA128L 27 SLOT=30;

pins ULTRA128L 28 SLOT=31;

pins ULTRA128L 29 SLOT=32;

pins ULTRA128L 30 SLOT=33;

functional SFTM


1 SLOT=2;


analog ICA 1;

analog HV_SRC 1;

pio PIO2 1 SLOT=3;

ieee IEEE_
NI 1;

power Fixed_P5 1 voltage=5.00, current=6.00;

power Fixed_P15 1 voltage=15.00, current=1.00;

power Fixed_N15 1 voltage=
-
15.00, current=1.00;

power PS 1 voltage=20.00, current=8.00, Slot=1;

power PS 2 voltage=20.00, current=8.00, Slot=2;

power PS 3

voltage=20.00, current=8.00, Slot=3;

power PS 4 voltage=20.00, current=8.00, Slot=4;

power PS 5 voltage=60.00, current=2.50, Slot=5;

power PS 6 voltage=60.00, current=2.50, Slot=6;

power PS 7 voltage=7.00, current=15.00, Slot=7;

power PS 8 voltage=7.00, c
urrent=15.00, Slot=8;

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ICT Quote Development Package:

The following list
s

of files are generally required by the providing vendor for Quotation
and Development purposes. Except where noted, all documents and files are obtained
from Agile.




Schematics in P
DF

Format



BOM in .CSV Format

downloaded from Agile



Assembly File Package

(includes cds2fab.txt


Fabmaster Extract File)



Fabrication File Package (includes Gerbers)



Test File Package (brd.txt, pad.txt, rte.txt, sym.txt and schematics in EDIF format)



.
TEL

N
etlist File (from PCB Release Directory)



@fixture.asc file from Fabmaster



@nails.asc file from Fabmaster



BSDL files



“BIN” file



Files required for generating Programmable Verification Test (Optional)


Note: Others might be requested from vendor.


Fixturing

Requirements Checklist:


To be completed
by fixture vendor
for ALL New Fixturing Projects.

Print last 4 pages of
this document and complete. Completed Checklist to be returned to Juniper Networks
Test Engineering.


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Fixture Inspect
ion Report For Juniper Networks


Fixture Name:






Date:

Evaluated By:






Assembly #:

Programming House
:





Fab #:

Manufacturer:






Manufacturer ID #:

Fixture Type:




Fi x t u r e Ch e c k l i s t

Pa s s

Fa i l


Component Clearance:



There must be least
0.050" clearance in both the X
-

and Y
-
directions between all
pressure fingers and board components or leads (including non
-
populated
locations).



There must be least 0.050" clearance in both the X
-

and Y
-
directions between all
bottom
-
side board stops and

board components or leads (including non
-
populated
locations)



There must be least 0.050" clearance in the X
-
, Y
-

and Z
-
directions between
bottom
-
side components and the top plate. This also applies to non
-
populated
components.



There must be least 0.
050" clearance in the X
-
, Y
-

and Z
-
directions between
bottom
-
side components and the probe plate (and any other support plates). This
also applies to non
-
populated components.



There must be sufficient clearance in the fixture lid to accommodate placemen
t
variations on large components (i.e. electrolytic caps, heatsinks, daughter boards,
etc). There must be at least 0.100" clearance between the top of any component and
the fixture lid when actuated. Ensure that clearance for electrolytic caps allows for
v
ariation in the angle of the component.



Provide documentation showing that the stack
-
up of the pressure finger height,
board thickness, and stopper height are correct. If it is necessary to counter
-
bore the
pressure fingers, provide calculations showing

the bore depth and proof that the
depth has been verified after the boring is completed.







Board Flatness:



Proper Board Stress Analysis is required for all designs. Please notify Juniper
Network if Probe Density exceeds prudent fixture design pr
actices.



There must be sufficient pressure fingers and board stops to keep the board flat.
There is no board flex allowed while the vacuum (or pneumatic) is being actuated.



PTH leads have sufficient clearance so they do not come into contact with the

top
plate (i.e. if milling of the top plate is required, ensure it is deep enough).






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Probe Requirements:



Probe travel (compression) is between .167" and .197". Documentation indicating
this check has been completed and must be supplied with t
he fixture. At a
minimum, the probe travel check must be performed in the center of the fixture,
each quadrant of the fixture, and in high density probe locations (>50 probes per ½"
square).



Top
-
side probes do not come into contact with the UUT until th
e vacuum or
pneumatic is actuated. This is to prevent bending the probes along the y
-
axis as the
lid is closed.



In general, it is the responsibility of the fixture vendor to decide which probe type
is best for a given target/application. However, we do
have the following
requirements:

?

Press
-
Fit Connector Locations:


With LITTLE 潲 NO lea搠Pr潴rusi潮o
Blade
“style 61”


Triad

“style 08”

o
Recommended Probe Force Table:

?

Standard Steel Probes:


0.100”


㔮㔠潺.


0.075”


㔮㔠潺.


0.050”


㐮㌠潺.


0.039”


㐮㌠潺.

?

Low Force
Probes (if required):


0.100”


㌮㔠潺.


0.075”


㌮ㄠ潺.


0.050”


㌮〠潺.


0.039”


㌮〠潺.



QA’s XProbe technology is preferred for 39 Mil Probing requirements.
Alternatively, “standard” 39 mil probes by QA (039
J
ㄶ⁓eriesF
.







Operation and
Mechanicals:



The fixture must actuate smoothly without binding and does not have any air leaks
or squeals. The board under test does not distort and remains flat during actuation.



The board will NOT fit in the fixture when rotated by 180°.



Impleme
nt “Cage” Guide Pins where required.



qhe fixture li搠assem扬y can 扥潣步搠潲atche搠 securely.



qhe center 潦 gravity must 扥⁷ithin the 潵tline 潦 the fixture 扡se t漠灲event the
fixt畲e fr潭 ti灰png.



dr潯oes E潲 channelsF sh潵l搠 扥⁣ut int漠 the

t潰o灬ate s漠ohe user can get their
fingers un摥r the e摧es 潦 the 扯br搠dt漠ma步 it easier t漠oem潶e the 扯br搠dr潭 the
fixt畲eF⸠ qhese gr潯oes sh潵l搠 扥 the l潮g e摧e 潦 the 扯br搠dear the t潯oi湧
灩ns.



rse bpa 摩ssi灡tive materials where a灰p潰oi
ate.



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Push Down/Supports are NOT allowed on the lids of BGA devices (in other words,
don’t push directly on the BGA devices
F 潲 any heat sin歳 that may 扥
m潵nte搠 潮t漠them.



cixtures sh潵l搠 扥⁤ signe搠 t漠all潷 f潲 eeat pin歳 that are⁡ttache搠to

摥vices⸠
This is 灲潶i摥搠that B潡r搠ptress mr潦iles all潷s f潲 this⸠ltherwiseⰠ 灬ease a摶ise
Juni灥r ketw潲歳 an搠we will ma步 arrangeme湴s t漠oave eeat pin歳 rem潶e搮



fm灬ement dr潵n搠mlane techni煵es where a灰p潰oiate t漠su灰pess n潩se an搠
enhance
signal integrity.







Safety:



When released from an angle of 45° or more, the fixture lid will remain in

the open position.



The fixture has a spring
-
loaded finger guard fitted to the interior to protect

against gas strut failure. This finger gua
rd has rounded edges.



Protection is in place to prevent an operator's finger from being pinched

between the fixture lid and the top plate as the vacuum is actuated.

o
All exposed corners have rounded edges in order to reduce the risks of

pinch
-
points.







Label Requirements:



All fixtures include these labels:

?

Fixture weight in both metric (kgs) and imperial (lbs) units.

?

Autofile number (3070 only).

?

Warning labels are placed on any non
-
ESD materials.

?

Board Name and Board Assembly Numbe
r Label.

?

If supplied, Capital Asset Label.







Documentation:



Proof of Compliance to specs.



Probe types and quantities documented.



Testjet / Opens Express plate sizes and quantities documented.



Pressure finger and board stop sizes and l
ocations documented. A map of pressure
finger locations should be provided (dxf format).



Provide a paper copy of the quality checks performed on the fixture.



Provide documentation showing the results of the wiring verification.



Probe plots, bottom

side board stop and milling, top side pressure fingers drawings
to be provided in electronic (dxf format).



Test coverage report.



Fixture Bom with manufacturers part numbers.






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Spare Parts and Additional Tools (provided w/ fixture):



Probes



Testjet plates




Pressure fingers and stoppers



Tooling pins



Gaskets



Shorting plate



Plexiglas plate (registration plate), with probing locations partially drilled. This
can double as a dust cover.



All fixtures to include Electron
ic Cycle Counter



Pressure finger validation plate with finger locations drilled out.



Plexiglas plate (~0.100" thick) that has been fully routed in the same

locations as the top plate.