Homework 3 CPRE 488 Embedded Systems Design Fall 2007 Due: Midnight Tuesday Oct. 2 on WebCT

sanatoriumdrumΗλεκτρονική - Συσκευές

25 Νοε 2013 (πριν από 3 χρόνια και 7 μήνες)

96 εμφανίσεις

Homework 3

CPRE 488 Embedded Systems Design

Fall 2007

Due: Midnight Tuesday Oct. 2 on WebCT


Name: Kyle Byerly

Section:C


Instructions: Write your answers in the spaces following each question. Submit the file
electronically onto WebCT. Use Microsoft Word

format; or contact the instructor for
compatibility if your will use another file format.


Late homework submission: A homework assignment will be accepted late for up to three
days past the due and is assessed with 10% per day penalty. Assignments later

than three
days past the due date will not be accepted. Contact the instructor in advance for a waiver
if you have a valid excuse, e.g. to travel for conference or job interview.


1.

[10] Q1
-
10. Show how a Set
-
speed command flows through the refined class
st
ructure described in Figure 1
-
18, moving from a change on the front panel on
the required changes on the train:

a.

Show it in the form of a collaboration diagram.

The following answer is
OK.


b.

Show it in the form of a sequence diagram.

The answer is OK.



2.

[1
0] Q1
-
15. Draw a class diagram for the classes required in a basic microwave
oven. The system should be able to set the microwave power level between 1 and
9 and time a cooking run up to 59 minutes and 59 seconds in one
-
second
increments. Include * classes

for the physical interface to the telephone line,
microphone, speakers, and buttons.

The answer is OK.


3.

[20] Q7
-
4: You are designing an accelerated system that performs the following
function as its main task:


for (i = 0; i < M; i++)


for (j = 0; j <

N; j++)


f[i][j] = (pix[i][j
-
1] + pix[i
-
1][j] + pix[i][j]


+ pix[i+1][j] + pix[i][j+1])/(5*MAXVAL);


Assume that the accelerator has the entire
pix

and
f

arrays in its internal
memory during the entire computation


pix

is read into the accelerato
r before
the operations begin and
f

is written out after all computations have been
completed.


a.

Show a system schedule for the host, accelerator, and bus assuming that the
accelerator is inactive during all data transfers. (All data are seen to the
acceler
ator before it starts and data are read from the accelerator after the
computations are finished.)
The answer is OK but the format is incorrect. The
format should follow Figure 7
-
18 on page 444, though the contents are much
simpler than that.

send pix

acce
lerate

read f

b.

Show a system schedule for the host, accelerator, and bus assuming that the
accelerator has enough memory for two
pix

and
f

arrays and that the host
can transfer data from one set of computations while another set is being
performed.

The answ
er is OK but again the format is incorrect.

send pix1

send pix2 and accelerate pix1 calculation

read f1 and accelerate pix2 calculation

read f2


4.

[10] What elements are there in an FPGA fabric? What are the typical types of
FPGA? Which type is the Xilinx Vi
rtex
-
II Pro FPGA family?


Elements: Logic blocks, interconnects, I/O and usually memory elements.

Types: SRAM, Antifuse, EPROM, EEPROM, Flash, Fuse.

Xilinx Virtex
-
II Pro FPGA are SRAM based technology.

Correct.


5.

[10] Which FPGA chip in the Xilinx Virtex
-
II Pro FPGA family is used in the
XUP boards? Go to the lab and find out the model number from the outside of the
chip, and then search the Xilinx web site to find out the number of logic cells
inside the chip.

Correct.


The XC2VP30 FPGA has 30,816 Logic
Cells

http://www.digilentinc.com/Products/Detail.cfm?Prod=XUPV2P&Nav1=Products&
Nav2=Pr