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MSc Project: References and Bibliography

137

X
-
R
EFERENCES AND
B
IBLIOGRAPHY


X.1

-

R
EFERENCES


[1]


Russell, G. and Ian L. Sayers, “
Advanced Simulation and Test Methodologies for VLSI
Design
”, London: Van Nostrand Reinhold (International), 1989, ISBN 0
-
7476
-
0001
-
5

[2]


Psarakis, M., D. Gizopoulos, A.
Paschalis, N. Kranitis and Y. Zorian, “
Robust and Low
-
Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers
”, VLSI
Test Symposium, 19th IEEE Proceedings on. VTS 2001, pp. 15
-
20, 2001

[3]

Gizopoulos, D., A. Paschalis and Y. Zorian,

An Effective Built
-
In Self
-
Test Scheme for
Parallel Multipliers
”, IEEE Trans. on Computers, vol. 48, no. 9, pp. 936
-
950, Sep. 1999

[4]


Raghunath, K. J., H. Farrokh, N. Naganathan, M. Rambaud, K. Mondal, F. Masci and
M. Hollopeter, “
A Compact Carry Save M
ultiplier Architecture and Its Applications
”,
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on, vol. 2,

pp. 794

797, 1998

[5]


Gizopoulos, D., A. Paschalis and Y. Zorian, “
Effective built
-
in self test for Booth
multipliers

, IEEE
Design & Test of Computers, vol. 15, no. 3, pp. 105
-
111, July
-
Sep.

1998

[6]

Weste N. H. E. and K. Eshragian, “
Principles of CMOS VLSI Design, A Systems
Perspective
”, Massachusetts: Addison
-
Wesley, 1993, ISBN 0
-
201
-
08222
-
5

[7]


Pirsch, P., “
Architectures
for Digital Signal Processing
”, Chichester: John Wiley &
Sons, 1998, ISBN 0
-
471
-
97145
-
6

[8]


Morling R. C. S. And I, Kale, lecture notes, “
DSP and Communication Processor
Design
”, MSc VLSI System Design, Univ. of Westminster, Feb. 2001

[9]


DSP Design Sli
des, Chapter 13
”, Lund University, accessed via Netscape, 12
nd

July
2001, at
http://www.tde.lth.se/ugradcourses/DSPDesign/slides/chap13.pdf

[10]

Omondi, A. R., “
Computer Arithmet
ic Systems Algorithms, Architecture and
Implementations
”, New Jersey: Prentice Hall, 1994,

ISBN 0
-
13
-
334301
-
4

[11]


Roth, C. H., “
Digital Systems Design Using VHDL
”, Boston: PWS, 1998, ISBN 0
-
534
-
95099
-
X


[12]


Pucknell, D. A. and K. Eshragian, “
Basic VLS
I Design
”, Australia: Prentice Hall, Third
Edition, 1994, ISBN 0
-
13
-
079153
-
9

MSc Project: References and Bibliography

138

[13]


Hurst, S. L., “
VLSI Testing, Digital and Mixed Analogue/Digital Techniques
”, London:
IEE Circuits, Devices and Systems Series 9, 1998, ISBN 0
-
85296
-
901
-
5

[14]


Bardell P. H.
, McAnney W. H. and Savir J., “
Built
-
In Test for VLSI: Pseudorandom
Techniques
”, New York: John Wiley & Sons, 1987, ISBN 0
-
471
-
62463
-
2

[15]


Lala, P. G., “
Digital Circuit Testing and Testability
”, San Diego: Academic Press, 1997,
ISBN 0
-
12
-
434330
-
9

[16]

El
dred, R.D., "
Test Routines Based on Symbolic Logical Statements
", Journal ACM,
vol.6, no.1, 1959, pp.33
-
36

[17]

Wu, C. W.,

EE6250: VLSI Testing and Design for Testability course notes, “
VLSI
Testing and Design for Testability, Chapter
-
3: Testability Measur
es”,

Department of
Electrical Engineering, National Tsing Hua University, Taiwan, accessed via Netscape,
11
th

Aug 2001, at
http://larc.ee.nthu.edu.tw/~cww/n/625/6250/03.pdf

[18]

Vemuri, R., E
CECS 682: VLSI Test and Validation course notes, “
Design for
Testability
”,Department of Electrical and Computer Engineering, University of
Cincinnati, Cincinnati, US,
, accessed via Netscape, 11
th

Aug 2001, at

http://www.ececs.uc.edu/~ranga/courses/682/slides
-
spring
-
2001/DFTnew.pdf

[19]

Goel, P., "
Test Generation Costs Analysis and Projections
", IEEE Proceedings on the
Design

Automation Conference, June 1980, pp. 77
-
84

[
20]

Mentor Graphics Corp., “
Fault Analysis User’s Manual: Software version V8.5_1
”,
Unpublished, Oregon, 1995

[21]

Mentor Graphics Corp., “
Synthesizing with Autologic II: Software version V8.5_1
”,
Unpublished, Oregon, 1995

[22]

Shah, S., A. J. Al
-
Khalili,
D. Al
-
Khalili, “
Comparison of 32
-
bit multipliers for various
performance measures
”,
Microelectronics, 2000, ICM 2000, Proceedings of the 12th
International Conference on, pp. 75


80, Nov. 2000

[23]

Kautz, W. H., “
Testing for Faults in Cellular Logic Arra
ys
”, proceedings of the 8
th

Annual Symposium on Switching and Automata Theory, pp. 161
-
174, 1967

[24]


Psarakis, M., D. Gizopoulos and A. Paschalis, “
Test Generation and Fault Simulation
for Cell Fault Model

Using Stuck at Fault Model Based Test Tools
”, E
lectronic Testing
Journal: Theory and Applications, vol. 13, no:3, Dec. 1998

[25]

Morling, R. C. S., “
Production Test of Digital Integrated Circuits
”, MSc VLSI System
Design, Univ. of Westminster, Dec. 2000



MSc Project: References and Bibliography

139

[26]


Friedman, A. D., “
Easily Testable Iterat
ive Systems
”, IEEE Trans. on Computers, vol.
C
-
22, no. 12, pp.1061
-
1065, Dec. 1973


(Theoretical Information about C
-
testability and iterative arrays)

[27]

Roth, J. P., “
Diagnosis of Automata Failures: A calculus and a method
”, IBM Journal
of Research and
Development, pp. 278
-
291, 1966

[28]

Eichelburger, E. B. and E. Lindbloom, “
Random Pattern Coverage Enhancement and
Diagnostics for LSSD Self
-
Test
”, IBM Journal of Research and Development, pp. 265
-
272, 1983



X.2

-

B
IBLIOGRAPHY



[1]


Bennets, R. G., “
Intr
oduction to Digital Board Testing
”, New York: Crane Russak,
1982, ISBN

8448
-
1385
-
0, pp. 107
-
114 & 220
-
223 & 165
-
172


(Information on Signature Analysis and Test Pattern Generation Problems)


[2]


Kaniz M., M. Cole and S. Mourad, “
Mentor Graphics Quickfaul
t II Tutorial
”,
Department of Electrical Engineering, Santa Clara University, Santa Clara, US,

accessed via Netscape, 27
th

July 2001, at
http://www.scudc.scu.edu/mentortu/mg_quickflt.html




(Quick to apply, but incomprehensive information about fault simulation)


[3]


Mentor Graphics Corp., “
SimView Common Simulation User’s Manual, Software
Version 8.5_1l
”, Unpublished, Oregon, 1995


(Worthy information about dofiles, waveform databases, sc
ripts and batch simulation)

[4]


Bhasker, J., “
A VHDL Primer
”, New Jersey: Prentice Hall, Revised Edition, 1995,
ISBN 0
-
13
-
181447
-
8


(Well presented information on VHDL for inexperienced users)

[5]

Naylor, D. and S. Jones, “
VHDL: A Logic Synthesis Approach
”, London: Chapman &
Hall, 1997, ISBN 0
-
412
-
61650
-
5


(Information about design


synthesis)


[6]


Morling R. C. S., “
Designing for Testability
”, MSc VLSI System Design, Univ. of
Westminster, Dec. 2000


(Very brief information on DfT and fault simulation t
erminology)